RISC-V Microprocessor IP
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64-bit High performance Quad Core RISC-V Microprocessor
- RISC-V 64G (RV64IMAFD) ISA
- 13-16 stage out-of-order pipeline implementation
- Advanced branch predictor: BTB, BHT, RAS
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64-bit RISC-V Single Core Microprocessor
- RISC-V 64G (RV64IMAFD) ISA
- 6 stage in-order pipeline implementation
- Advanced branch predictor: BTB, BHT, RAS
- Harvard architecture
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32b/64b RISC-V 2-stage, scalar, in-order, Embedded Processor. RTOS and multi-core capable. Maps upto ARM M-4F. Optimal PPA.
- 32-bit RISC-V core
- 2-stage pipeline
- Available in many versions: RV32I[M][C][F][B][P][U]
- 32/16 general purpose registers
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32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
- 32/64 Bit RISC-V core
- 5-stage pipeline
- In-order, Single issue
- Multicore Capable (up to 8 cores)
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TESIC RISC-V CC EAL5+ Secure Element Soft/Hard Macro
- CC EAL5+ secure microcontroller system
- CC EAL5+ secure cryptography
- CC EAL5+ security sensors
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AXI Bus Display Controller
- Wide range of programmable Display Panel resolutions:
- Releases supporting baseline display requirements and releases with following
- optional display processing features:
- Color Palette RAM per layer or single Palette for integrated display image
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Display Controller - LCD / OLED Panels (AXI4 Bus)
- Wide range of programmable Display Panel resolutions:
- High-Resolution Display Panel support features by AXI4 Protocol:
- Releases supporting baseline display requirements and advanced releases with following optional display processing features:
- Overlay Windows option comes with advanced composition features:
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Display Controller - LCD / OLED Panels (AXI Bus)
- Wide range of programmable Display Panel resolutions:
- Releases supporting baseline display requirements and advanced releases with following optional display processing features:
- Overlay Windows option comes with advanced composition features:
- Color Palette RAM per layer or single Palette for integrated display image
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AXI Subsystem
- Subsystem for microprocessors with 32-bit AMBA®AXI4 Interfaces, such as: BA2x, and Several RISC-V processors
- Integrated Modules: AXI Multi-Layer Interconnect, Multichannel DMA, SRAM Controller, External parallel flash controller, and APB Subsystem (APB-SBS) (I2C, SPI, UART. GPIO, RTC. Timer, WDT, and PIC)
- Highly configurable and customizable
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AHB Subsystem
- Subsystem for microprocessors with 32-bit AMBA® 3.0 AHB-Lite or AHB Interfaces, such as: BA2x, ARM Cortex-M0/M1M3/M4, and Several RISC-V processors
- AHB-SBS-BASE integrates: AHB Multi-Layer Interconnect, xSPI Controller, SRAM Controller, and APB Subsystem (APB-SBS) (I2C, SPI, UART. GPIO, RTC. Timer, WDT, and PIC)
- AHB-SBS-EXT adds: Multichannel DMA, SPI-to-AHB bridge, and External parallel flash or SRAM controller
- Highly configurable and customizable
