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Post-Quantum IP

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Compare 28 IP from 14 vendors (1 - 10)
  • APB Post-Quantum Cryptography Accelerator IP Core
    • Implements ML-KEM and ML-DSA post-quantum cryptography digital signature standards. The system interface is an microprocessor slave bus (APB, AHB, AXI options are available).
    • The design is fully synchronous and requires only minimal CPU intervention due to internal microprogramming sequencer.
    Block Diagram -- APB Post-Quantum Cryptography Accelerator IP Core
  • Post-Quantum Key Encapsulation IP Core
    • The PQC-KEM is an IP Core for ML-KEM Key Encapsulation that supports key generation, encapsulation, and decapsulation operations for all ML-KEM variants standardized by NIST in FIPS 203.
    • ML-KEM is a post-quantum cryptographic (PQC) algorithm, designed to be robust against a quantum computer attack.
    Block Diagram -- Post-Quantum Key Encapsulation IP Core
  • Crypto Coprocessor with integrated Post-Quantum Cryptography IPs
    • The Crypto Coprocessors are a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA or ASIC.
    • Symmetric operations are offloaded very efficiently as it has a built-in scatter/gather DMA. The coprocessors can be used to accelerate/offload IPsec, VPN, TLS/SSL, disk encryption, or any custom application requiring cryptography algorithms.
    Block Diagram -- Crypto Coprocessor with integrated Post-Quantum Cryptography IPs
  • Unified Hardware IP for Post-Quantum Cryptography based on Kyber and Dilithium
    • Turn-key implementations of the NIST FIPS recommended CRYSTALS post-quantum for key encapsulation (KEM) and digital signature algorithm (DSA)
    Block Diagram -- Unified Hardware IP for Post-Quantum Cryptography based on Kyber and Dilithium
  • Post-Quantum Cryptography IP: Crystals Kyber - Crystals Dilithium - XMSS - LMS
    • 512 and/or 768 and/or 1024-bit secret key length
    • Implementation protected against Side-Channel Attacks (Key Generation and Key Decapsulation operations are sensitive):
    • Hybrid hardware-software tunable solution
    • Tunable in performance or power/area
  • Post-Quantum Cryptography Processor
    • PQPlatform-CoPro (PQP-HW-COP) adds PQShield’s state-of-the-art post-quantum cryptography (PQC) to your security sub-system, with optional side-channel countermeasures (SCA).
    • PQPlatform-CoPro can be optimized for minimum area as part of an existing security sub-system.
    • PQPlatform-CoPro is designed to be run by an existing CPU in your security system, using PQShield’s supplied firmware.
    Block Diagram -- Post-Quantum Cryptography Processor
  • Lattice-based Post-Quantum Cryptography Processing Engine
    • PQC(post-quantumcryptography) engine
    • NISTSP800-56Acomplaint
    • NISTFIPS186-4and186-5compliant
    • ANSSIX9.142-2020compliant
    Block Diagram -- Lattice-based Post-Quantum Cryptography Processing Engine
  • Hash-based post-quantum hardware accelerator
    • Power side-channel secure (SCA) Keccak engine
    • AXI4-Lite (64-bit 1x subordinate)
    • NIST FIPS-202 SHA3-224/256/384/512
    Block Diagram -- Hash-based post-quantum hardware accelerator
  • IoT device security platform with a hybrid post-quantum cryptographic algorithm
    • Software development lifecycle integration (SDLC, CI/CD)
    • Key and certificate management (PKI/CLM)
    • On-device security features (e.g. secure boot, flash encryption)
    • On-device key generation & storage
    Block Diagram -- IoT device security platform with a hybrid post-quantum cryptographic algorithm
  • Dilithium IP Core
    • Dilithium IP Core is a post-quantum digital signature algorithm (DSA).
    • It currently supports Sign and Verify functions, with key generation functionality planned for future implementation.
    • This IP is compliant with Dilithium specification submitted on round 3 of NIST Post-Quantum Cryptography Standardization process.
    Block Diagram -- Dilithium IP Core
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