IP Catalog > PSRAM Controller

PSRAM Controller IP

Filter
Filter

Login required.

Sign in

Search (11)
Compare 11 IP from 9 vendors (1 - 10)
  • AP Memory UHS PSRAM Controller
    • This controller supports AP Memory’s UHS series of high speed PSRAM devices which can clock frequencies of upto 1066 MHz.
    • This controller enables smooth integration of APMemory’s UHS OPI PSRAM memory device chips into various new-gen devices made with mobile and wearable low power SoCs’.
    • This memory controller implementation is designed to give the user full flexibility for driving the memory control signals and timing adjustment for data sampling.
    Block Diagram -- AP Memory UHS PSRAM Controller
  • Octal SPI DDR PSRAM controller
    • This controller supports AP Memory’s Xccela open standard Bus for digital interconnect and data communications, suitable for non-volatile and volatile memories such as PSRAM.
    • This controller enables smooth integration AP memory’s of Xccela PSRAM memory chips into various new-gen devices made with mobile and wearable low power SoCs’.
    • This memory controller implementation is designed to give the user full flexibility for driving the memory control signals and timing adjustment for data sampling.
    Block Diagram -- Octal SPI DDR PSRAM controller
  • PSRAM UHS Controller
    • Compliant with the following specifications:
    • DTI PSRAM UHS Controller supports:
  • AHB Octal SPI Controller with PSRAM and XIP Support
    • The Octal SPI Memory Controller IP core is a serial peripheral interface (SPI) master which controls an external serial device, usually an industry-standard FLASH or PSRAM memory device.
    • In Software Mode, an AHB Master may access the register interface of the Controller to implement a wide range of protocol variants and/or commands on the SPI bus.
    Block Diagram -- AHB Octal SPI Controller with PSRAM and XIP Support
  • Expanded Serial Peripheral Interface (xSPI) Slave Controller
    • The JESD251 Expanded Serial Peripheral Interface Slave controller is provides high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface(SPI) devices
    • It is used to connect xSPI Master devices in computing, automotive, Internet of Things, Embedded system and mobile system processor to non-volatile memories, graphics peripherals, networking peripherals,FPGAs, sensors devices
    Block Diagram -- Expanded Serial Peripheral Interface (xSPI) Slave Controller
  • Expanded Serial Peripheral Interface (xSPI)Master Controller
    • The Expanded Serial Peripheral Interface (JESD251) Master controller is low signal count, high data bandwidth, primarily for use in computing, automotive, Internet of Things, Embedded system and mobile system processor to connect multiple source of Serial Peripheral Interface (xSPI) slave devices like non-volatile memories, graphics peripherals, networking peripherals,FPGAs, sensors devices
    Block Diagram -- Expanded Serial Peripheral Interface (xSPI)Master Controller
  • PSRAM/RPC PHY & Controller
    • The DDR IP Mixed-Signal MR PSRAM PHY and RPC PHY provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible PSRAM/RPC devices
    • It is optimized for low-power and high-speed applications with robust timing and small silicon area
    • The PSRAM PHY supports AP memory UHS/OPI PSRAM components on the market, and the RPC PHY supports ETRON components on the market
    Block Diagram -- PSRAM/RPC PHY & Controller
  • High Speed PSRAM Solution
    • High Speed PSRAM Solution
    • ? High Speed PSRAM PHY
    • ? Operating range of 200MHz (400Mbps) to 533MHz (1066Mbps) in PSRAM mode
    • ? PHY Utility Block (PUBL) component
    Block Diagram -- High Speed PSRAM Solution
  • xSPI - PSRAM Master
    • SPI Protocol:
    • AXI4 Slave
    • AXI4 DMA Master
    • AXI4 – LITE SLAVE
    Block Diagram -- xSPI - PSRAM Master
  • xSPI, HyperBus™, and Xccela™ Serial Memory Controller
    • The xSPI-MC core is a versatile serial/SPI memory controller, which allows a system to easily detect and access the attached memory device or directly boot from it.
    • The controller core supports most of the proprietary SPI protocols used by Flash and PSRAM device vendors and is compatible to JEDEC’s eXpanded SPI (xSPI), HyperBus™ and Xccela™ standards.
    Block Diagram -- xSPI, HyperBus™, and Xccela™ Serial Memory Controller
×
Semiconductor IP