Phy IP

This IP includes a recommendation-compliant 802.11ax PHY layer C floating-point code for the Station (STA) mode.
The code is integrated into a simulation environment that allows the configuration of mandatory features and the performance evaluation in terms of frame error rate.
It is designed to generate fixed-point sequences in order to accelerate the development of both C fixed-point code and HDL code for prototyping environments.

The DDR PHY IP is a combination of hard macro, I/O Pad and synthesizable RTL to provide a physical interface to JEDEC standard DDR3/DDR4 SDRAM memories.
The synthesizable RTL (ddr_phy_top) provides control functions such as initialization, SDRAM interface training, impedance calibration and programmable configuration controls.

The USB PHY IP is UTMI interface compatible and a dedicated circuit for full-function USB 2.0 transceivers.
It is a mixed-signal circuit, with the analog part including the transmitting and receiving circuits, level conversion circuits, bus driver circuits, etc., and the digital part including the transmitting and receiving and speed switching control circuits, encoding and decoding circuits, serial-to-parallel and parallel-to-serial conversion circuits, as well as digital CDR circuits, etc.

This IP integrates both xSPI (Expanded Serial Peripheral Interface) and eMMC 5.1 PHY (Physical Layer) into a single unified solution, enabling support for two distinct memory protocols within the same IP.
By combining the PHY layers for both interfaces, the design simplifies system integration, reduces area and pin count, and enhances design flexibility for SoCs that require both boot and high-speed storage functionality.

IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face advanced package.
This GUCIe PHY not only supports UCIe specification rev 1.1 compliance physical layer and Raw D2D interface (RDI) but also optionally provides the