IP Catalog > PHY

PHY IP

Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (4,013)
Compare 4,013 IP from 197 vendors (1 - 10)
  • TSMC CLN5FF GUCIe LP Die-to-Die PHY
    • IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face advanced package.
    • This GUCIe PHY not only supports UCIe specification rev 1.1 compliance physical layer and Raw D2D interface (RDI) but also optionally provides the
    Block Diagram -- TSMC CLN5FF GUCIe LP Die-to-Die PHY
  • USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
    • Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
    • Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
    • x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
    • Low active and standby power
    • Small area for low silicon cost
    Block Diagram -- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
  • USB4 PHY - TSMC N4P 1.2V, North/South Poly Orientation
    • Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
    • Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
    • x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
    • Low active and standby power
    • Small area for low silicon cost
    Block Diagram -- USB4 PHY - TSMC N4P 1.2V, North/South Poly Orientation
  • USB4 PHY - TSMC N3E 1.2V, North/South Poly Orientation
    • Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
    • Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
    • x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
    • Low active and standby power
    • Small area for low silicon cost
    Block Diagram -- USB4 PHY - TSMC N3E 1.2V, North/South Poly Orientation
  • USB4 PHY - TSMC N3P 1.2V, North/South Poly Orientation
    • Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
    • Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
    • x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
    • Low active and standby power
    • Small area for low silicon cost
    Block Diagram -- USB4 PHY - TSMC N3P 1.2V, North/South Poly Orientation
  • DDR3 and DDR4 Controller and PHY on TSMC 12nm
    • This DDR3/4 IP combo solution presented, is meticulously designed for high performance and low power consumption, utilizing sophisticated architecture and advanced technology.
    • Fabricated in TSMC’s 12nm CMOS process, this solution includes both controller and PHY IPs, providing comprehensive support for DDR3 and DDR4 memory interfaces.
    Block Diagram -- DDR3 and DDR4 Controller and PHY on TSMC 12nm
  • HBM4E PHY and controller
    • Advanced clocking architecture minimizes clock jitter
    • DFI PHY Independent Mode for initialization and training
    • IEEE 1500 interface, memory BIST feature, and loop-back function
    • Supports lane repair
    Block Diagram -- HBM4E PHY and controller
  • DDR5 MRDIMM PHY and Controller
    • The DDR5 12.8Gbps MRDIMM Gen2 PHY and controller memory IP system solutions double the performance of DDR5 DRAM.
    • The DDDR5 12.8Gbps design and architecture address the need for greater memory bandwidth to accommodate unprecedented AI processing demands in enterprise and data center applications, including AI in the cloud.
    Block Diagram -- DDR5 MRDIMM PHY and Controller
  • MIPI C/D Combo TX PHY and DSI controller
    • High Data Rates: Supports data transmission rates
    • Energy Efficiency: Optimized for low power consumption, making it ideal for battery-powered devices
    • Complete Solution: Combines the MIPI CD-PHY Transmitter PHY and DSI Controller to make it a one-stop solution
    • Flexible IP Configuration




      •  
    •  
    •  
×
Semiconductor IP