PCI Express 7.0 IP
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IDE Security IP Modules for PCI Express 7.0
- Full support of PCI Express 7.0 (64GT/s) IDE specification
- High-performance AES-GCM based packet encryption, decryption, authentication
- Seamless integration with Synopsys controllers via TLP/FLIT packet-based interface
- FLIT mode support
- Support for PCIe 7.0, 6.0, 5.0, 4.0 and 3.1 data rates
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Controller IP for PCI Express 7.0
- Supports all required features of the PCI Express 7.0 (128 GT/s) specification
- Allows a full 128GT/s x16 lane bandwidth with up to 1024-bit data path implementations
- Supports advanced RAS data protection features including ECC
- Advanced RAS-DES features for simplified bring-up and debug
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PCI Express Gen3 SERDES PHY on Samsung 28LPP
- Programmable SERDES analog front end that supports 1 to 8 Gbps standard serial protocols
- Compact form factor – 0.134 mm2 active silicon area per lane including ESD
- Industry leading low power – typically 7.0 mW/Gbps including termination
- Minimal latency – 3 UI between parallel transfer and serial transmission
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PCIe 7.0 Controller with AXI
- Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
- Separate native TX/RX data path separating posted/Non posted/completion traffic
- Handles up to 4 TLPs per cycle
- Advanced PIPE modes and port bifurcation
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PCIe 7.0 Controller
- Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
- Separate native TX/RX data path separating posted/Non posted/completion traffic
- Handles up to 4 TLPs per cycle
- Advanced PIPE modes and port bifurcation
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PCIe 7.0 Integrity and Data Encryption (IDE) Security IP Module
- Full support of PCI Express 7.0 (64GT/s) IDE specification
- High-performance AES-GCM based packet encryption, decryption, authentication
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PCIe 7.0 Controller (can be configured to support EP, RP, DM, or SW applications)
- Supports all required features of the PCI Express 7.0, 6.x, 5.0, 4.0, 3.1, 2.1, and 1.1 specifications