PCI Express 3.0 IP
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117
IP
from 14 vendors
(1
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10)
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PCI Express Gen3/Enterprise Class SERDES PHY on Samsung 28LPP
- Industry leading low power PMA macro – 88mW per lane at 8Gbps (11.0 mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
- Compact form factor – 0.216 mm2 active silicon area per lane including ESD
- Enterprise class Long Reach 5-tap DFE supporting beyond standard PCIe Channels
- Minimal latency – 3 UI between parallel transfer and serial transmission
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PCI Express Gen3 SERDES PHY on Samsung 7LPP
- Industry leading low power PMA macro – 36mW per lane at 8Gbps (4.5mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
- Compact form factor – 0.1 mm2 active silicon area per lane including ESD
- Minimal latency – 3 UI between parallel transfer and serial transmission
- Single-lane macro scalable to unlimited link width – x1, x2, x4, x8, x16, etc.
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PCI Express Gen3 / SATA3 SERDES PHY on Samsung 28FDSOI
- Programmable SERDES analog front end that supports 1 to 8 Gbps standard serial protocols
- Compact form factor – 0.165 mm2 active silicon area per lane including ESD
- Industry leading low power – typically 6.5 mW/Gbps including termination
- Finely configurable receiver impedance, CTLE gain and bandwidth, with fully adaptive CTLE and DFE
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Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)
- Compliant with the PCI Express Base Specification 3.0
- Supported Lane width: x1, x2, x4 and x8
- Fully compliant with PCI Express transaction ordering rules
- Optimal buffering for high bandwidth Direct Memory Access (DMA) applications
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PCIe 3.0 PHY, UMC 28HPC x4, North/South (vertical) poly orientation
- Compliant with the PCI Express (PCIe®) 3.1, 2.1, 1.1 and PIPE specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
- L1 substate and SRIS support
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PCIe 3.0 PHY, UMC 28HPC x1, North/South (vertical) poly orientation
- Compliant with the PCI Express (PCIe®) 3.1, 2.1, 1.1 and PIPE specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
- L1 substate and SRIS support
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PCIe 3.0 PHY, TSMC N4P x2, North/South (vertical) poly orientation
- Compliant with the PCI Express (PCIe®) 3.1, 2.1, 1.1 and PIPE specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
- L1 substate and SRIS support
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PCIe 3.0 PHY, TSMC 28HPM x16, North/South (vertical) poly orientation
- Compliant with the PCI Express (PCIe®) 3.1, 2.1, 1.1 and PIPE specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
- L1 substate and SRIS support
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PCIe 3.0 PHY, TSMC 12FFCP x2, North/South (vertical) poly orientation
- Compliant with the PCI Express (PCIe®) 3.1, 2.1, 1.1 and PIPE specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
- L1 substate and SRIS support
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PCIe 3.0 PHY, SS SF5A, North/South (vertical) poly orientation
- Compliant with the PCI Express (PCIe®) 3.1, 2.1, 1.1 and PIPE specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
- L1 substate and SRIS support
