Pci express 3.0 IP

The PCIe 3.0 (Peripheral Component Interconnect Express 3.0) is a computer hardware interface standard that is used to connect various components to a computer's motherboard.
It is the third generation of the PCIe standard and offers increased bandwidth, improved performance, and reduced power consumption compared to its predecessor, PCIe 2.0 Overall, PCIe 3.0 provides faster and more efficient communication between the various components in a computer, including graphics cards, network adapters, and storage devices, resulting in better overall performance.

The Scalable Switch Intel® FPGA IP for PCI Express is a fully configurable switch that implements one fully configurable upstream port and connectivity for up to 64 downstream ports.

Industry leading low power PMA macro – 88mW per lane at 8Gbps (11.0 mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
Compact form factor – 0.216 mm2 active silicon area per lane including ESD
Enterprise class Long Reach 5-tap DFE supporting beyond standard PCIe Channels
Minimal latency – 3 UI between parallel transfer and serial transmission

Industry leading low power PMA macro – 36mW per lane at 8Gbps (4.5mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
Compact form factor – 0.1 mm2 active silicon area per lane including ESD
Minimal latency – 3 UI between parallel transfer and serial transmission
Single-lane macro scalable to unlimited link width – x1, x2, x4, x8, x16, etc.

Programmable SERDES analog front end that supports 1 to 8 Gbps standard serial protocols
Compact form factor – 0.165 mm2 active silicon area per lane including ESD
Industry leading low power – typically 6.5 mW/Gbps including termination
Finely configurable receiver impedance, CTLE gain and bandwidth, with fully adaptive CTLE and DFE

The USB 3.0 Device Upgrade provides a dedicated dual simplex, routable packet architecture for USB3.0 packet transfers, with a disable option for power savings.
The USB 3.0 Upgrade IP supports all power management features as well as a dedicated link manager for each downstream port for increased efficiency.

Compliant with the PCI Express (PCIe®) 3.1, 2.1, 1.1 and PIPE specifications
x1, x2, x4, x8, x16 lane configurations with bifurcation
Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
L1 substate and SRIS support

Compliant with the PCI Express (PCIe®) 3.1, 2.1, 1.1 and PIPE specifications
x1, x2, x4, x8, x16 lane configurations with bifurcation
Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
L1 substate and SRIS support

PCI Express 3.0 IP