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Mixel MIPI D-PHY IP

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Compare 80 IP from 1 vendors (1 - 10)
  • MIPI D-PHY Universal IP
    • Complies with MIPI Standard for D-PHY V1.0
    • Point-to-point differential interface supporting multiple data lanes and a clock lane
    • Supports both high speed and low-power modes
    • Data lanes support both bidirectional and unidirectional modes
    Block Diagram -- MIPI D-PHY Universal IP
  • MIPI D-PHY CSI-2 TX (Transmitter) IP
    • Consists of 1 Clock lane and 4 Data lanes
    • Complies with MIPI Standard 1.0 for D-PHY
    • Supports both high speed and low-power modes
    • 80 Mbps to 1Gbps data rate in high speed mode
    Block Diagram -- MIPI D-PHY CSI-2 TX (Transmitter) IP
  • MIPI D-PHY DSI RX (Receiver) IP
    • Consists of 1 Clock lane and 2 Data lanes
    • Complies with MIPI Standard 1.0 for D-PHY
    • Supports both high speed and low-power modes
    • 80 Mbps to 1Gbps data rate in high speed mode
    Block Diagram -- MIPI D-PHY DSI RX (Receiver) IP
  • MIPI D-PHY DSI TX (Transmitter) IP
    • Consists of 1 Clock lane and 4 Data lanes
    • Complies with MIPI Standard 1.0 for D-PHY
    • Supports both high speed and low-power modes
    • 80 Mbps to 1Gbps data rate in high speed mode
    Block Diagram -- MIPI D-PHY DSI TX (Transmitter) IP
  • MIPI D-PHY CSI-2 RX (Receiver) IP
    • Consists of 1 Clock lane and 2 Data lanes
    • Complies with MIPI Standard 1.0 for D-PHY
    • Supports both high speed and low-power modes
    • 80 Mbps to 1Gbps data rate in high speed mode
    Block Diagram -- MIPI D-PHY CSI-2 RX (Receiver) IP
  • MIPI D-PHY IP 4.5Gbps in TSMC N7
    • Supports MIPI Alliance Specification for D-PHY Version 2.5
    • Consists of 1 Clock lane and 4 Data lanes
    Block Diagram -- MIPI D-PHY IP 4.5Gbps in TSMC N7
  • MIPI D-PHY Universal IP in TSMC 28HPC+
    • Supports MIPI Alliance Specification for D-PHY Version 2.5
    • Consists of 1 Clock lane and 4 Data lanes
    • Embedded, high performance, and highly programmable PLL
    Block Diagram -- MIPI D-PHY Universal IP in TSMC 28HPC+
  • MIPI D-PHY Universal IP in TSMC 40ULP
    • Consists of 1 Clock lane and up to 2 Data lanes.
    • Supports MIPI® Alliance Specification for D-PHYSM Version 1.1.
    Block Diagram -- MIPI D-PHY Universal IP in TSMC 40ULP
  • MIPI D-PHY Universal IP in TSMC 65GP
    • Supports MIPI Alliance Specification for D-PHY Version 2.1
    • Backward compatible with MIPI Specifications for D-PHY v1.2, and v1.1
    • Consists of 1 Clock lane and 4 Data lanes
    Block Diagram -- MIPI D-PHY Universal IP in TSMC 65GP
  • MIPI D-PHY Universal IP in TSMC 22ULP
    • Consists of 1 Clock lane and up to 4 Data lanes.
    • Supports MIPI® Alliance Specification for D-PHY Version 2.1.
    • Supports both high speed and low-power modes.
    Block Diagram -- MIPI D-PHY Universal IP in TSMC 22ULP
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