Menta IP

Compare 3 IP from 2 vendors (1 - 3)

eFPGA IP - 100% third party standard cells
- Every element of the eFPGA can be defined in numbers: logic cells, adaptive DSP (with and without FIR engine, add & mult size, amount), RAM (type and amount) and IOs.
- In addition, Menta eFPGA IP Cores being 100% standard cells based, multiple power / performances trade-off can be achieved based on customer requirements.
- The eFPGA IP Cores are provided as hard IPs (GDSII).
- Menta eFPGA IP Cores use standard cells, and as such integrate smoothly into any standard ASIC design flow. Designers use RTL as the input to our software Origami Programmer to generate the eFPGA program file (bitstream) and obtain accurate performance evaluation.
eFPGA IP as a synthesizable RTL core
- Support of any technology node, foundry and process option
- High LUTs density
- Support of any kind of arithmetic block right within the IP
AVC/H.264 Baseline encoder core
- ISO/IEC 14496-10 (MPEG-4 Part 10), AVC/H.264 Compliant video encoder
- Baseline Profile support
- Single core max. frame resolution up to 2048x2048
- I and P frame types supported