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MIPI DSI-2 TX Controller IP

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  • MIPI DSI-2 TX Controller
    • Compliant with the following specifications:  MIPI DSI-2 Specification v1.1, MIPI D-PHY Specification v2.0, 4 D-PHY data lanes, Display Command Set (DCS) Specification v1.3 and APB Specification v3.0
    •  Supports ULPS/LPDT/BTA mode
    Block Diagram -- MIPI DSI-2 TX Controller
  • MIPI DSI-2 Transmitter v1.1 Controller IP, Compatible with MIPI D-PHY & C-PHY
    • Compliant with MIPI DSI-2 Standard v0.8.x, MIPI D-PHY Standard v1.x, MIPI D-PHY Standard V2.x and MIPI C-PHY V1.x
    • Up to 3 Gsps per trio using C-PHY. 17Gbps in 3 Trios
    • Up to 2.5 Gbps per data lane of D-PHY (V2.0). 10Gbps in 4 Lanes
    • Programmable 1, 2, 3 (C-PHY) or 4 (D-PHY) Data Lane Configuration
    Block Diagram -- MIPI DSI-2 Transmitter v1.1 Controller IP, Compatible with MIPI D-PHY & C-PHY
  • MIPI DSI-2 Controller Core
    • Fully DSI-2 standard compliant
    • 64 and 32 bit core widths
    • Host (Tx) and Peripheral (Rx) versions
    • 1-8, 2.5+ Gbit/s D-PHY data lane support
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Semiconductor IP