MIPI DSI-2 Transmitter v1.1 Controller IP, Compatible with MIPI D-PHY & C-PHY
Overview
MIPI is the Mobile Industry Processor Interface that provides specification for software and hardware interfaces in mobile terminals and thereby encouraging the adoption of these standards throughout the industry chain for achieving interoperability has come up with many specifications like CSI, DSI, DPHY, CPHY, MPHY, SoundWire, UniPro and more. The MIPI Display Serial Interface (DSI) is an interface between a display or any other data interface, and a host processor baseband application engine. This interface is defined by the MIPI Alliance, which lays down a series of modules required in a MIPI compliant product. MIPI DSI Receiver is leveraged by mobile and high–speed serial applications as a controller for receiving video, command or user data, transmitted via MIPI DSI Transmitter over MIPI lines. It is sent to the next, higher level for subsequent processing. The MIPI DSI Receiver, along with MIPI DSI Transmitter and MIPI DPHY, provides a complete solution for MIPI DSI communication.
Key Features
- Compliant with MIPI DSI-2 Standard v0.8.x, MIPI D-PHY Standard v1.x, MIPI D-PHY Standard V2.x and MIPI C-PHY V1.x
- Up to 3 Gsps per trio using C-PHY. 17Gbps in 3 Trios
- Up to 2.5 Gbps per data lane of D-PHY (V2.0). 10Gbps in 4 Lanes
- Programmable 1, 2, 3 (C-PHY) or 4 (D-PHY) Data Lane Configuration
- Forward and reverse communication
- Configurable virtual channel up to 4
- Function in continuous and non-continuous clock modes
- Support for command and video mode
- Support for burst and non-burst modes
- Support for pulse and event modes
- Color modes: 16, 18, 24 and 36 bpp
- Support for display stream compression (dsc)
Benefits
- Highly modular and configurable design
- Layered architecture
- Active low async reset
- Clearly de-marked clock domains
- Extensive clock gating support
Block Diagram
Applications
- Wearables
- Consumer
- Automotive
Deliverables
- Configurable RTL Code
- HDL-based test bench and behavioral models
- Test cases
- Protocol checkers, bus watchers, and performance monitors
- Configurable synthesis shell
- Documentation
- Design guide
- Verification guide
- Synthesis guide
Technical Specifications
Foundry, Node
Independent, suitable to all 3rd party PHY's
Maturity
In Production
Availability
Immediate
Related IPs
- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI C-PHY v1.1
- MIPI C-PHY V1.1 TSMC 28nm HPC+
- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)