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Legacy-Compatible 8051 IP

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Compare 8 IP from 5 vendors (1 - 8)
  • Ultra-Small 8051-Compatible Microcontroller
    • The T8051XC3 core implements one of the smallest-available 8-bit MCS®51-compatible microcontrollers.
    • The core integrates an 8051 CPU with a serial communication controller, flexible timer/counter, multi-purpose I/O port, interrupt controller, and optionally with a debug unit supporting JTAG and Single-Wire interfaces. 
    Block Diagram -- Ultra-Small 8051-Compatible Microcontroller
  • Legacy-Configurable 8051-Compatible Microcontroller IP
    • Fully compatible with the MCS® 51 instruction set
    • Configurable CPU architecture: 12, 6, or 4 clock cycles per machine cycle
    • Extensive set of optional features and peripherals
    • JTAG-based On-Chip Debug Support (OCDS)
    Block Diagram -- Legacy-Configurable 8051-Compatible Microcontroller IP
  • I3C - Function Controller
    • The I3c protocol, short for " Improved Inter - Integrated Circuit," is a communication protocol designed to improve upon the widely - used I2C protocol.
    • It was developed by the MIPI Alliance, a global organization that aims to develop interface specifications for mobile devices.
    Block Diagram -- I3C - Function Controller
  • M8051EW V3.0+ Fast 8-bit Microcontroller with on-chip debug
    • Binary and Memory cycle compatible with the Intel 8051•
    • Optional conditional branch acceleration
    • Up to eight 16-bit data pointers
    • 25-input, five level interrupt controller
    Block Diagram -- M8051EW V3.0+ Fast 8-bit Microcontroller with on-chip debug
  • Enhanced Fast 8-bit Microcontroller
    • Binary and Memory cycle compatible with Intel 8051 Designs
    • Fast 2-clocks per machine cycle implementation
    • 1Mbyte program and data address spaces
    • Memory interfaces may be configured for synchronous or asynchronous devices
  • Enhanced Fast 8-bit Microcontroller with On-Chip Debug
    • Binary and Memory cycle compatible with Intel 8051 Designs
    • Fast 2-clocks per machine cycle implementation
    • Richly-featured hardware debugger: multiple breakpoints, instruction traceback, single step execution. Full debug access to all registers and memory spaces 1Mbyte program and data address spaces
    • Memory interfaces may be configured for synchronous or asynchronous devices
  • ONFI 4.0 NAND Flash Controller & PHY
    • • Support ONFI 4.0, EZ – NAND, Standard ClearNAND, Advanced ClearNAND
    • • Support standard asynchronous NAND flash
    • • High performance from 40MT/s to 800MT/s
    • • High density NAND flash up to 1024 Gb
    Block Diagram -- ONFI 4.0 NAND Flash Controller & PHY
  • M8051W V 5.0 Fast 8-bit Microcontroller
    • Binary and Memory cycle compatible with Intel 8051 Designs
    • Fast 2-clocks per machine cycle implementation
    • 1Mbyte program and data address spaces
    • Memory interfaces may be configured for synchronous or asynchronous devices
    Block Diagram -- M8051W V 5.0 Fast 8-bit Microcontroller
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