Enhanced Fast 8-bit Microcontroller

Overview

The M8051EW is a highly configurable soft-core implementation of the industry standard 8051 microcontroller that features a two-clocks-per-machine cycle architecture. Use of standard synchronous design methodology makes this core simple to integrate into both ASIC and FPGA SoC designs.

Key Features

  • Binary and Memory cycle compatible with Intel 8051 Designs
  • Fast 2-clocks per machine cycle implementation
  • 1Mbyte program and data address spaces
  • Memory interfaces may be configured for synchronous or asynchronous devices
  • External interfaces support wait states
  • Optional demultiplexed program and data interfaces
  • Optional single machine cycle memory accesses
  • Up to 8 16-bit data pointers
  • 25-input, five level interrupt controller
  • Full implementation of legacy peripherals: 32 GPIO ports, 3 16-bit counter timers and a full-duplex serial port. All legacy peripherals are optional
  • Watchdog timer
  • 2-wire and 4-wire interfaces
  • Pulse width modulator array
  • Flexible interfacing options for external peripherals
  • Power saving modes: powerdown, stasis , idle and run

Deliverables

  • VHDL 93 and Verilog 2001 RTL source code
  • RTL configuration script
  • VHDL and Verilog Testbenches
  • Demonstration assembly code
  • Simulation scripts for Modelsim and Cadence
  • Synopsys synthesis compile scripts and SDC timing constraint files
  • Example Mentor DFT and ATPG scripts
  • Example netlist implementation with SDF files
  • Detailed product specification and a user guide containing implementation notes

Technical Specifications

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Semiconductor IP