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ISO 26262 RISC-V Processor IP

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  • 32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification
    • Flexible use cases
    • roven technology
    • State-of-the-art safety and security



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    Block Diagram -- 32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification
  • 8-stage superscalar processor that supports ISO 26262 ASIL (Automotive Safety Integrity Level) -D level functional safety for automotive applications
    • 32-bit in-order dual-issue 8-stage pipeline CPU architecture
    • AndeStar™ V5 Instruction Set Architecture (ISA)
    • 16/32-bit mixable instruction format for compacting code density
    • Advanced low power branch predication to speed up control code
    • Return Address Stack (RAS) to accelerate procedure returns
    Block Diagram -- 8-stage superscalar processor that supports ISO 26262 ASIL (Automotive Safety Integrity Level) -D level functional safety for automotive applications
  • Embedded Hardware Security Module (Root of Trust) - Automotive Grade ISO 26262 ASIL-B
    • The RT-64x Embedded Hardware Security Module (Root of Trust) family are fully programmable, ISO 26262 ASIL-B hardware security cores offering security by design for automotive applications.
    • They protect against a wide range of failures such as permanent, transient and latent faults and hardware and software attacks with state-of-the-art anti-tamper and security techniques.
    Block Diagram -- Embedded Hardware Security Module (Root of Trust) - Automotive Grade ISO 26262 ASIL-B
  • 32 Bit - Embedded RISC-V Processor Core
    • Best-in-class performance for small-area and low-power applications
    • Highly configurable and easy and quick to customize and verify
    • Process compliant with ISO 26262 and ISO 21434
    Block Diagram -- 32 Bit - Embedded RISC-V Processor Core
  • Embedded HSM Family (Root of Trust) - Automotive Grade ISO 26262 ASIL-B
    • Custom-designed 32-bit RISC-V secure processor
    • Security model include hierarchical privilege model, secure key management policy, hardware-enforced isolation/access control/protection, error management policy
    • Standard hardware cryptographic accelerators, including AES (all modes), HMAC, SHA-2 (all modes), RSA up to 4096 bits, ECC up to 521 bits, a NIST-compliant Random Bit Generator, AXI Multi Issue Out-of-Order, and Fast DMA capability. Additional algorithms such as Whirlpool (SHE), SHA-1 (legacy), AES-CMAC, SHA-3, Poly1305, ChaCha and OSCCA SM2-3-4 are available
    • Multi-layered security model protects all core components against a wide range of attacks
    Block Diagram -- Embedded HSM Family (Root of Trust) - Automotive Grade ISO 26262 ASIL-B
  • 32-bit Embedded RISC-V Functional Safety Processor
    • The EMSA5-FS is a processor core designed for functional safety.
    • The fault-tolerant processor uses dual or triple instances of the EMSA5, an efficient 32-bit embedded processor IP core implementing the RISC-V Instruction Set Architecture (ISA).
    Block Diagram -- 32-bit Embedded RISC-V Functional Safety Processor
  • Quantum Safe, ISO 21434 Automotive-grade Programmable Hardware Security Module
    • The automotive-grade CryptoManager RT-7xx v3 Root of Trust family is the next generation of fully programmable ISO 26262 and ISO 21434 compliant hardware security modules offering Quantum Safe security by design for secure automotive applications.
    • The CryptoManager RT-7xx family protects against a wide range of hardware and software attacks through state-of-the-art side channel attack countermeasures and anti-tamper and security techniques.
    Block Diagram -- Quantum Safe, ISO 21434 Automotive-grade Programmable Hardware Security Module
  • ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core
    • D23-SE processor core certified by parts 2, 4, 5, 7, 8 and 9 of the standards, meeting the architectural metrics and random hardware fault metrics requirements for ASIL B/D 
    • D23-SE supports split-mode that 2 cores could run independently when split-lock is configured. ECC for memory soft error protection; bus protection to protect bus transaction; core trap status bus interface provides real time information of trap status from core.
    Block Diagram -- ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core
  • ARC-V RMX Series Functional Safety Processor IP
    • Developed for full ASIL D compliance (systematic and random faults)
    • Tightly-coupled dual-core safety implementation based on ultra-compact ARC-V RMX processors
    • Single solution support for safety level up to ASIL D; Supports both ASIL D lockstep operation or ASIL B single-core operation (RMX-510-FS only)
    • Integrated hardware safety features including ECC, user-programmable windowed watchdog timer, end-to-end protection (E2E) for buses/data-path, and lockstep safety monitor
    Block Diagram -- ARC-V RMX Series Functional Safety Processor IP
  • Integrated Secure Element (iSE) for high-end devices with HW isolated secure processing
    • Services:
    • Secure Boot
    • Secure Firmware update
    • Life-cycle management
    Block Diagram -- Integrated Secure Element (iSE) for high-end devices with HW isolated secure processing
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