HMC IP
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9
IP
from 5 vendors
(1
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9)
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Xilinx HMC Controller
- Fully compliant with Hybrid Memory Cube Specification Revision 1.x
- Support 10 Gb/s, 12.5 Gb/s, 15 Gb/s SerDes I/O interface
- Support either GTH or GTY transceiver use
- Support both HMC link modes
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1-15G SERDES PCIe3/HMC SERDES PHY - TSMC 16FF+GL
- TSMC 16FF+GL
- Low Power
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Multi Standard programmable SERDES PHY with single/multi-lane configurations with support of long-reach channel
- Single SERDES Design that meets wide range of Standards, Protocols and Speeds.
- Any combination is possible, e.g. USB-3.0, PCIe Gen-3 and SATA Gen-3 in a single Combo SERDES.
- Internal Low Jitter PLL support the various standards clocking requirements- no need for additional components.
- Flexible Design- Tile Based Design that enable customer to select any number of Tx and Rx Lanes.
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UltraScale FPGAs Transceivers Wizard
- Creates customized protocol presets to configure high-speed serial transceivers in UltraScale FPGAs
- Protocol presets provided for 10GBASE-R, 10GBASE-KR, 3G-SDI, Aurora 8B/10B, Aurora 64B/66B, CAUI-4, CAUI-10, CEI-11G, CPRI™, Gigabit Ethernet, HD-SDI, HMC, Interlaken, JESD204B, MoSys Bandwidth Engine, OTL 4.10, OTU2/2e, OTU4, QSGMII, RXAUI, SATA, Serial RapidIO Gen2, XAUI, XLAUI, and DisplayPort.
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12.5G Multi-SerDes PHY
- Reference Clock:
- Internal PLL:
- Data Transmit:
- Data Receive:
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25G Multi-SerDes PHY
- Reference Clock:
- Internal PLL:
- Data Transmit:
- Data Receive:
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32G Multi-SerDes PHY
- Reference Clock:
- Internal PLL:
- Data Transmit:
- Data Receive:
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Driver Amplifier operating from 24-30 GHz and can be used in wide band application or to drive the high-power amplifier
- RF Frequency: 24-30 GHz
- Gain of 13.6 dB
- Output P1dB of 24.9 dBm
- Noise Figure of 3 dB
