HMC Memory Model

Overview

HMC Memory Model provides an smart way to verify the HMC component of a SOC or a ASIC. The SmartDV's HMC memory model is fully compliant with standard HMC Specification and provides the following features. Better than Denali Memory Models.

HMC Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

HMC Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports 100% of HMC protocol standard 1.0,2.0 and 2.1
Supports all the HMC commands as per the specs.
Quickly validates the implementation of the HMC standard.
Supports 2,4 and 8 link configuration
Supports half_width(8-lanes) and full_width(16-lanes)
Supports 16, 32, 48, 64, 80, 96, 112, 128 and 256 byte request
Supports 12.5 Gb/s, 15 Gb/s, 25 Gb/s, 28 Gb/s, or 30 Gb/s SerDes I/O interface
Supports Packet-based data/command interface
Supports Poison packets handling
Supports scrambler and descrambler
Supports Training Sequence
Supports lane reversal and polarity inversion
Supports all block size setting
Supports flow control
Supports link retraining
Supports packet retry
Checks for following

Check-points include power up,initialization and power off rules,
State based rules, Active Command rules.
Read/Write Command rules etc.
All timing violations.

Various types of error injection support
Supports write data mask and data strobe features.
Supports 4GB/8GB configuration
Supports Internal ECC data correction and Error detection (cyclic redundancy check [CRC]) for packets with automatic retry
Supports Power management supported per link
Supports Built-in self-test (BIST)
Supports JTAG interface (IEEE 1149.1-2001, 1149.6)
Supports I2C interface up to 1 MHz
Supports SPI master interface
Supports all timing delay ranges in one model: min, typical and max.
Constantly monitors HMC behavior during simulation.
Protocol checker fully compliant with HMC Specification 1.0,2.0 and 2.1.
Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
Built in functional coverage analysis.
Supports Callbacks, so that user can access the data observed by monitor.

Benefits

Faster testbench development and more complete verification of HMC designs.
Easy to use command interface simplifies monitor control and configuration.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the HMC testcases.
Complete UVM/OVM sequence library for HMC controller.
Examples showing how to connect and usage of Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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