FPU IP
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FPU Verification IP
- Compliant to RISC-V Specification and IEEE 754 floating point standard.
- Configurable bits (half, single, double and quad precision).
- Supports all RISC-V Floating point instructions (ADD, SUB, MUL, DIV, SQRT, comparison, and conversion between float and int).
- Supports the rounding modes defined by RISC-V.
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MCU core with high-performance FPU (32 or 64 bit)
- Harvard architecture (separate instruction and data buses)
- RV32IMCF[DA] or RV64IMCF[DA] ISA
- User and Machine privilege modes
- High-performance IEEE 754-2008 compliant floating-point unit
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Half Precision IEEE-754R complete FPU for graphics processing
- Configurable for width
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ARC EM22FS safety processor
- Dual-core lockstep safety processor supports ISO 26262 automotive safety standards
- Single solution support for safety level up to ASIL D; Supports both ASIL D lockstep operation or ASIL B single core operation
- Includes hardware safety features such as ECC, integrated user-programmable windowed watchdog timer, and lockstep safety monitor
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Scalar and SIMD floating point option for the ARC HS5x, HS5xD and HS6x processors
- Dual-issue, 64-bit processors for high-performance embedded applications
- 52-bit physical and 64-bit virtual addressing
- Up to 5400 DMIPS and 11,088 CoreMark per core at 1.8 GHz on 16FFC (worst case conditions, single-core configuration
- Multicore Processor versions with up to 12 CPU cores and up to 16 hardware accelerators
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Memory management unit (MMU) option for ARC HS5x and HS6x processors
- Dual-issue, 64-bit processors for high-performance embedded applications
- 52-bit physical and 64-bit virtual addressing
- Up to 5400 DMIPS and 11,088 CoreMark per core at 1.8 GHz on 16FFC (worst case conditions, single-core configuration
- Multicore Processor versions with up to 12 CPU cores and up to 16 hardware accelerators
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L2 cache/cluster shared memory option for multicore versions of ARC HS5x and HS6x processors
- Dual-issue, 64-bit processors for high-performance embedded applications
- 52-bit physical and 64-bit virtual addressing
- Up to 5400 DMIPS and 11,088 CoreMark per core at 1.8 GHz on 16FFC (worst case conditions, single-core configuration
- Multicore Processor versions with up to 12 CPU cores and up to 16 hardware accelerators
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ARC HS68MP multi-core version of dual-issue HS68 processor with MMU, ARCv3 ISA, for embedded Linux applications
- Dual-issue, 64-bit processors for high-performance embedded applications
- 52-bit physical and 64-bit virtual addressing
- Up to 5400 DMIPS and 11,088 CoreMark per core at 1.8 GHz on 16FFC (worst case conditions, single-core configuration
- Multicore Processor versions with up to 12 CPU cores and up to 16 hardware accelerators
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ARC HS68 64-bit, dual-issue processor with MMU, ARCv3 ISA, for embedded Linux applications
- Dual-issue, 64-bit processors for high-performance embedded applications
- 52-bit physical and 64-bit virtual addressing
- Up to 5400 DMIPS and 11,088 CoreMark per core at 1.8 GHz on 16FFC (worst case conditions, single-core configuration
- Multicore Processor versions with up to 12 CPU cores and up to 16 hardware accelerators
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ARC HS66MP multi-core version of dual-issue HS66 with I and D cache for high-performance embedded applications
- Dual-issue, 64-bit processors for high-performance embedded applications
- 52-bit physical and 64-bit virtual addressing
- Up to 5400 DMIPS and 11,088 CoreMark per core at 1.8 GHz on 16FFC (worst case conditions, single-core configuration
- Multicore Processor versions with up to 12 CPU cores and up to 16 hardware accelerators
