IP Catalog > FPU

FPU IP

Filter
Filter

Login required.

Sign in

Search (72)
Compare 72 IP from 17 vendors (1 - 10)
  • FPU Verification IP
    • Compliant to RISC-V Specification and IEEE 754 floating point standard.
    • Configurable bits (half, single, double and quad precision).
    • Supports all RISC-V Floating point instructions (ADD, SUB, MUL, DIV, SQRT, comparison, and conversion between float and int).
    • Supports the rounding modes defined by RISC-V.
    Block Diagram -- FPU Verification IP
  • MCU core with high-performance FPU (32 or 64 bit)
    • Harvard architecture (separate instruction and data buses)
    • RV32IMCF[DA] or RV64IMCF[DA] ISA
    • User and Machine privilege modes
    • High-performance IEEE 754-2008 compliant floating-point unit
    Block Diagram -- MCU core with high-performance FPU (32 or 64 bit)
  • ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core
    • D23-SE processor core certified by parts 2, 4, 5, 7, 8 and 9 of the standards, meeting the architectural metrics and random hardware fault metrics requirements for ASIL B/D 
    • D23-SE supports split-mode that 2 cores could run independently when split-lock is configured. ECC for memory soft error protection; bus protection to protect bus transaction; core trap status bus interface provides real time information of trap status from core.
    Block Diagram -- ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core
  • ARC EM22FS safety processor
    • Dual-core lockstep safety processor supports ISO 26262 automotive safety standards
    • Single solution support for safety level up to ASIL D; Supports both ASIL D lockstep operation or ASIL B single core operation
    • Includes hardware safety features such as ECC, integrated user-programmable windowed watchdog timer, and lockstep safety monitor
    Block Diagram -- ARC EM22FS safety processor
  • Scalar and SIMD floating point option for the ARC HS5x, HS5xD and HS6x processors
    • Dual-issue, 64-bit processors for high-performance embedded applications
    • 52-bit physical and 64-bit virtual addressing
    • Up to 5400 DMIPS and 11,088 CoreMark per core at 1.8 GHz on 16FFC (worst case conditions, single-core configuration
    • Multicore Processor versions with up to 12 CPU cores and up to 16 hardware accelerators
    Block Diagram -- Scalar and SIMD floating point option for the ARC HS5x, HS5xD and HS6x processors
  • Memory management unit (MMU) option for ARC HS5x and HS6x processors
    • Dual-issue, 64-bit processors for high-performance embedded applications
    • 52-bit physical and 64-bit virtual addressing
    • Up to 5400 DMIPS and 11,088 CoreMark per core at 1.8 GHz on 16FFC (worst case conditions, single-core configuration
    • Multicore Processor versions with up to 12 CPU cores and up to 16 hardware accelerators
    Block Diagram -- Memory management unit (MMU) option for ARC HS5x and HS6x processors
  • L2 cache/cluster shared memory option for multicore versions of ARC HS5x and HS6x processors
    • Dual-issue, 64-bit processors for high-performance embedded applications
    • 52-bit physical and 64-bit virtual addressing
    • Up to 5400 DMIPS and 11,088 CoreMark per core at 1.8 GHz on 16FFC (worst case conditions, single-core configuration
    • Multicore Processor versions with up to 12 CPU cores and up to 16 hardware accelerators
    Block Diagram -- L2 cache/cluster shared memory option for multicore versions of ARC HS5x and HS6x processors
  • ARC HS68MP multi-core version of dual-issue HS68 processor with MMU, ARCv3 ISA, for embedded Linux applications
    • Dual-issue, 64-bit processors for high-performance embedded applications
    • 52-bit physical and 64-bit virtual addressing
    • Up to 5400 DMIPS and 11,088 CoreMark per core at 1.8 GHz on 16FFC (worst case conditions, single-core configuration
    • Multicore Processor versions with up to 12 CPU cores and up to 16 hardware accelerators
    Block Diagram -- ARC HS68MP multi-core version of dual-issue HS68 processor with MMU, ARCv3 ISA, for embedded Linux applications
  • ARC HS68 64-bit, dual-issue processor with MMU, ARCv3 ISA, for embedded Linux applications
    • Dual-issue, 64-bit processors for high-performance embedded applications
    • 52-bit physical and 64-bit virtual addressing
    • Up to 5400 DMIPS and 11,088 CoreMark per core at 1.8 GHz on 16FFC (worst case conditions, single-core configuration
    • Multicore Processor versions with up to 12 CPU cores and up to 16 hardware accelerators
    Block Diagram -- ARC HS68 64-bit, dual-issue processor with MMU, ARCv3 ISA, for embedded Linux applications
×
Semiconductor IP