ECC IP
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BCH ECC Core IP
- The patent-pending Dynamically Configurable BCH technology is the base for the BCH ECC engine incorporating BCH coders and decoders configurable for a wide range of code-length for high performance and high data rate error corrections.
- The BCH ECC engine with configurable code-length BCH coders and decoders performs the Inversion-less Berlekamp-Massey Algorithm (IBMA) to generate or decode the ECC code on each clock.
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Elliptic Curve Cryptography IP
- Supported algorithms:
- Point multiplication
- ECDSA signature generation
- ECDSA signature verification
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Hamming Code ECC
- Encoder:
- Decoder
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high-performance solution for elliptic curve cryptography
- Supported algorithms:
- Supported Elliptic Curves
- Optional Side Channel Attacks countermeasures
- Input/Output EC point verification
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NIST P-256/P-384 ECDH+ECDSA - Compact ECC IP Cores supporting ECDH and ECDSA on NIST P-256/P-384
- Minimal Resource Requirements
- Secure Architecture
- FIPS 186-4 and SP 800-56A compliant
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ECC with BCH Algorithm
- High bandwidth, low latency parallel encode and decode paths
- Configurable number of encode blocks
- Configurable number of decode blocks
- Configurable code word length (K), up to 1024 bytes
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100% Secure Cryptographic System for RSA, Diffie-Hellman and ECC with AMBA AHB, AXI4 and APB
- For RSA, Diffie-Hellman and ECC
- With AMBA AHB, AXI4 and APB
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Error Correction Checking (ECC) Core
- Supports Single Bit Error correction and double bit error detection functions
- Supports hamming algorithm for 4 to 64 data widths
- Supports Hsiao algorithm for 4 to 128 data widths
- Supports encode only, decode only and encode/decode modes
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Attack resistant ECC hardware acceleration core
- Supports any EC over GF(p) of the simplified Weierstrass form that is commonly defined in ECC standards such as NIST, SEC2, Brainpool