Die-on-Die Interface PHY IP
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36
IP
from 11 vendors
(1
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10)
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TSMC CLN6FF/7FF Die-to-Die Interface PHY
- 32 full-duplex lanes per slice
- 8 slices are included in analog hard macro
- Lane repair
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TSMC CLN5FF Glink 2.0 Die-to-Die PHY
- 32 full-duplex lanes per slice
- 8 slices are included in analog hard macro
- VALID and READY handshake mechanism
- Flow control between TX and RX
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TSMC CLN3FFE GLink 2.3LL Die-to-Die PHY
- 56 full-duplex lanes per slice
- 6-Slice/2-Slice PMA included in the analog hard macro
- Lane repair
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TSMC CLN5FF GLink 2.0 Die-to-Die PHY
- 32 full-duplex lanes per slice
- 8 slices are included in the analog hard macro
- 1:8 mode with 256-bit data width or 1:16 mode with 512-bit data width for user interface
- VALID and READY handshake mechanism
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TSMC CLN5FF GLink 2.3LL Die-to-Die PHY
- 56 full-duplex lanes per slice
- 8 slices are included in the analog hard macro
- 1:8 mode with 448-bit data width or 1:16 mode with 963-bit data width for user interface
- VALID and READY handshake mechanism
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TSMC CLN7FF GLink-3D Die-to-Die Slave PHY
- Supports SoIC (3DFabric) CoW and WoW assembly
- Supports face to face and face to back with the same GDSII
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TSMC CLN5FF GLink-3D Die-to-Die Master PHY
- Supports SoIC (3DFabric) CoW and WoW assembly
- Supports face to face and face to back with the same GDSII
- Supports point to multi-point (multi-Slave) communication
- Up to 5 Gbps/bond (2.5 GHz DDR) data rate
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Ultralink Controller
- 1Tbps/mm unidirectional bandwidth
- Low power and low latency
- Easy routing and straightforward integration
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Die-to-Die PHY
- 64 data lanes with configuration and bump map layout dependent on the PHY type (UCIe, BoW, UMI, SBD)
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UCIe Controller baseline for Streaming Protocols
- Low latency controller for UCIe-based multi-die designs
- Includes Die-to-Die Adapter layer and Protocol layer
- Supports on-chip interconnect fabrics including AXI, CHI C2C, CXS, PCIe, CXL, and streaming
- Error detection and correction with optional CRC and retry functionality
