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DMA Controller IP

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Compare 325 IP from 72 vendors (1 - 10)
  • AMBA AHB 4 Channel DMA Controller
    • AMBA® AHB Master/Slave DMA Controller
    • Four DMA Channels
    • Internal Arbitration for Single AHB Master Interface
    • Memory to Memory. Memory to Peripheral, Peripheral to Memory, Peripheral to Peripheral modes
    Block Diagram -- AMBA AHB 4 Channel DMA Controller
  • AHB Single Channel DMA Controller
    • AHB Master/Slave DMA Controller
    • Single Channel – multiple instantiation
    • Memory to Memory, Memory to Peripheral, Peripheral to Memory, Peripheral to Peripheral modes
    • Source and destination address descriptors
    Block Diagram -- AHB Single Channel DMA Controller
  • Multi-channel DMA Controller
    • Selectable 8237 Mode
    • Configurable up to 16 Independent DMA Channels for Non-8237 Mode
    • Configurable Data Width of 8, 16, 32 or 64 Bits for Non-8237 Mode
    • Configurable Address Width of 16, 24 or 32 Bits for Non-8237 Mode
    Block Diagram -- Multi-channel DMA Controller
  • 8237 DMA Controller
    • 24-bit length address register
    • 16-bit length count register
    • 4 independent DMA channels
    • 4 clock / 1 bus cycle
    Block Diagram -- 8237 DMA Controller
  • Scatter-Gather DMA Controller
    • Supports up to 16 physical channels
    • Up to 8 sub-channels per physical channel
    • Four priority levels using round-robin arbitration (weighted or simple)
    • WISHBONE bus widths from 8 to 128 bits
    Block Diagram -- Scatter-Gather DMA Controller
  • AXI4 Multi-Channel DMA Controller
    • 1 - 16 Multi-Channel High Performance DMA Controller Engines:
    • Up to 16 DMA transfers in parallel active
    • Hardware or Software Initiated Transfers
    • Link-List Processor for Autonomous & Chained Block Transfers
  • AHB Multi-Channel DMA Controller
    • 1 - 16 Multi-Channel High Performance DMA Controller Engines:
    • High-Speed Finite State Machine Control
    • High Throughput to/from Memory & Peripherals via AMBA AHB on both small and large data sets
    • Configurable with Dual-Port, Single- or Dual-Clock FIFO
  • ULL PCIe DMA Controller
    • PCIe Gen 3 (x16)
    • Ultra-fast transfer of data between FPGA logic and memory mapped user space
    • Multi-channel circular buffer architecture
    • Zero-copy circular buffers memory mapped to user space
  • Direct memory access (DMA) controller
    • Tiny Heterogenous Processing
    • System-wide Security
    • Highly Configurable Feature Set
  • DMA Controller with TileLink IP
    • Supports Single channel DMA Transmit and DMA Receive Engine
    • Supports access for Ring and Chained Descriptor Structures
    • Configurable Transmit and Receive Engine based on Host Memory Data Width
    • Configurable support by DMA Transmit and Receive Engine for both of the endianness of the host memory (Little / Big Endian)
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Semiconductor IP