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DMA Controller IP

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Search (392)
Compare 392 IP from 78 vendors (1 - 10)
  • AHB/AXI/Wishbone DMA Controller
    • The AXI4-SGDMA IP core implements a Host-to-Peripheral (H2P), or a Peripheral-to-Host (P2H) Direct Memory Access (DMA) engine, which interfaces the host system with an AXI4 Memory-Mapped master port and the peripheral with either a slave or a master AXI4-Stream port.
    • The core operates in either Scatter-Gather (SG) Mode, reading descriptors from a run-time defined memory mapped-location, or in Direct Mode, transferring data according to a descriptor stored in local registers.
    Block Diagram -- AHB/AXI/Wishbone DMA Controller
  • DMA Controller with TileLink IIP
    • Supports 1-16 channel DMA Transmit and DMA Receive Engine
    • Compliant with TileLink specification v1.7.1
    • Supports access for Ring and Chained Descriptor Structures
    • Configurable Transmit and Receive Engine based on Host Memory Data Width
    Block Diagram -- DMA Controller with TileLink IIP
  • DMA Controller with OCP IIP
    • Supports 1-16 channel DMA Transmit and DMA Receive Engine
    • Compliant with OCP 3.1 specification
    • Supports access for Ring and Chained Descriptor Structures
    • Configurable Transmit and Receive Engine based on Host Memory Data Width
    Block Diagram -- DMA Controller with OCP IIP
  • DMA Controller with AXI IIP
    • Supports 1-16 channel DMA Transmit and DMA Receive Engine
    • Supports latest ARM AMBA 3/4 AXI, AXI4-Lite, AMBA4 ACE, AMBA4 ACE-Lite, AXI4-Stream specification.
    • Supports access for Ring and Chained Descriptor Structures
    • Configurable Transmit and Receive Engine based on Host Memory Data Width
    Block Diagram -- DMA Controller with AXI IIP
  • DMA Controller with AHB IIP
    • Supports 1-16 channel DMA Transmit and DMA Receive Engine
    • Compliant with ARM AMBA 2 AHB Specification
    • Optional support for AMBA 3 AHB-Lite and AMBA 5 AHB Specification
    • Supports access for Ring and Chained Descriptor Structures
    Block Diagram -- DMA Controller with AHB IIP
  • ULL PCIe DMA Controller
    • PCIe Gen 3 (x16)
    • Ultra-fast transfer of data between FPGA logic and memory mapped user space
    • Multi-channel circular buffer architecture
    • Zero-copy circular buffers memory mapped to user space
  • Direct memory access (DMA) controller
    • Tiny Heterogenous Processing
    • System-wide Security
    • Highly Configurable Feature Set
  • AHB Scatter-Gather DMA Controller
    • Memory-based, linked-list transfer descriptors.
    • 3 descriptor sizes to balance functionality and setup overhead.
    • Configurable number of channels.
    • Configurable number of peripherals (up to 64).
  • AHB Single Channel DMA Controller
    • The AHB Single Channel DMA Controller core is a configurable single channel direct memory access controller.
    • The DMA IP Core is a Verilog HDL design that can be used in ASIC, Structured ASIC and FPGA designs.
    • The design is intended to be used with AMBA based systems as a controller to transfer data directly from system memory to memory or system memory to peripheral device or IP Core.
    Block Diagram -- AHB Single Channel DMA Controller
  • AMBA AHB 4 Channel DMA Controller
    • The AHB 4 Channel DMA Controller is a multiple-channel direct memory access controller.
    • The DMA IP Core is a Verilog HDL design that can be used in ASIC, Structured ASIC and FPGA designs.
    • The design is intended to be used with AMBA based systems as a controller to transfer data directly from system memory to memory or system memory to peripheral device or IP Core.
    Block Diagram -- AMBA AHB 4 Channel DMA Controller
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Semiconductor IP