The eSi-SG-DMA core can be used to implement 1D and 2D memory-to-memory, memory-to-peripheral, peripheral-to-memory and peripheral-to-peripheral data transfers, with scatter and gather functionality.
As well as linked-list based memory copies, the DMA can be programmed to perform memory set/zero, endian conversion, deinterleaving, matrix transpose and other transforms as well as CRC and IP checksum calculation during transfers.
The core features 3 AMBA AHB-lite interfaces, to easily be integrated in to any CPU subsystem.
AHB Scatter-Gather DMA Controller
Overview
Key Features
- Memory-based, linked-list transfer descriptors.
- 3 descriptor sizes to balance functionality and setup overhead.
- Configurable number of channels.
- Configurable number of peripherals (up to 64).
- Programmable X and Y count, increment, access size and burst length.
- CRC and IP checksum calculation.
- AMBA 3 AHB-lite slave interface for control register access.
- Dual AMBA 3 AHB-lite master interfaces for simultaneous read and write.
Deliverables
- Verilog RTL
- Testbench
- Simulation and synthesis scripts
- Documentation
- C API
Technical Specifications
Maturity
Silicon proven in multiple products
Availability
Immediate