Direct memory access (DMA) controller

Overview

The Arm CoreLink DMA-350 direct memory access (DMA) controller offloads memory movement tasks from the CPU to improve system performance and energy-efficiency. It includes support for scatter gather, 2D transformations, memory to memory, memory to peripheral (and vice versa) transfers.

CoreLink DMA-350 is a highly configurable IP based on the AMBA AXI5 protocol with support for eight channels, two AXI manager interfaces, Arm TrustZone technology, and other advanced features. This DMA controller pairs well with the Cortex-M55 processor in endpoint AI systems to populate the tightly coupled memory (TCM) with data efficiently for ML and signal processing. CoreLink DMA-350 also supports integration into systems based on Arm Cortex-A and Cortex-R CPUs and can be easily programmed via an AMBA 4 APB interface.

Key Features

  • Tiny Heterogenous Processing
    • Channels support an optional AXI stream interface for connecting custom logic for in-line data processing. Examples include color-space conversion or alpha blending. Powerful data processing can be achieved with high efficiency in a small footprint.
  • System-wide Security
    • Supports Arm TrustZone for Cortex-M and Cortex-A, so that data movement respects security attributes. DMA-350 embraces security by design, and is helpful to those looking to achieve PSA Certified.
  • Highly Configurable Feature Set
    • Designed to be extremely flexible and meet a wide variety of use cases, from small sensors to complex SoCs. Many features are configurable, so designers can optimize the IP block for specific requirements.

Technical Specifications

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Semiconductor IP