Dma IP

The DMU signals to the attached DMA Controller (DMA request) when there is a newly received message available at one of the attached M_CAN's Rx FIFOs respectively when there is the possibility to load a new Tx message into the M_CAN's Tx FIFO/Queue.
The DMA controller then autonomously transfers the received message from the M_CAN's Message RAM to the System Memory or the message to be transmitted from the System Memory to the M_CAN's Message RAM.

The MC-SDMA IP core implements a highly configurable, bandwidth-efficient, and easy-to-use Direct Memory Access (DMA) controller that transfers data between the host system’s memory and multiple peripherals equipped with streaming interfaces.
The core interfaces with the host memory via a manager AMBA^® AXI4 (memory-mapped) port and provides access to its configuration and status registers (CSRs) via a subordinate AXI4-Lite or APB4 interface.

The PCI Express specification allows endpoints that incorporate several physical PCIe functions that share the same PCIe connection. Such endpoints are called multi-function devices.
The big advantage of a multi-function device is, that a separate device driver can be associated to each physical function.
This simplifies driver development and maintenance significantly by separating the peripheral functions logically into different device drivers.

The Multi-Channel AXI DMA engine IP Core for AXI4 is a powerful programmable AXI Stream to AXI memory mapped bridge with sophisticated data addressing options.
These features allow data accesses on a tile basis in order to address regions of interest (ROI) based applications like stereo cameras, 2D picture compression algorithms and others.

The AXI Bridge with DMA IP core is the ultimate PCIe DMA IP solution with a powerful mix of multiple industry standard AXI Interfaces.
AXI Stream interfaces allow continuous data streaming from FPGA to Host or from Host to FPGA. S-AXI Memory mapped interfaces allow easy data access of remote memories in order to realize shared memory access or per to peer applications.

The Multichannel DMA IP for PCI Express provides high efficiency, speed, and configuration flexibility to support various applications from HPC, cloud, networking, to embedded
With support for up to 2048 channels and Linux-based PCIe drivers provided, this low latency, low resource utilization solution is essential in handling movements of large volumes of data to optimize system performance.

The memory 2 memory DMA controller transfers data from one memory location to another memory location.
DMA operation begins when software enables a DMA, after setting the source and destination starting addresses, transfer count, and control information.
The DMA engine moves the data block, and the DMA operation ends naturally when the number of bytes specified by the transfer count has been moved

The Advanced Encryption Standard (AES) IP Core is a complete hardware implementation encryption/decryption algorithm described in the U.S. Government Federal Information Processing Standards Publication 197 (FIPS 197).
The AES IP Core implements the Rijndael algorithm which is a symmetric block cipher that can process 128-bit data blocks using 128, 192, or 256-bit cipher keys.

The Scatter-Gather DMA Engine Verification IP (VIP) is designed to validate the functionality and performance of scatter-gather DMA controllers in SoCs. It ensures efficient data transfer between non-contiguous memory regions while minimizing CPU utilization, offering features like protocol compliance and transaction monitoring.
Ideal for applications such as networking, multimedia, storage, and embedded systems, the VIP helps ensure high-performance, reliable data movement. It supports multi-channel configurations, error injection, and performance monitoring to optimize system efficiency and robustness

The AXI4-SGDMA IP core implements a Host-to-Peripheral (H2P), or a Peripheral-to-Host (P2H) Direct Memory Access (DMA) engine, which interfaces the host system with an AXI4 Memory-Mapped master port and the peripheral with either a slave or a master AXI4-Stream port.
The core operates in either Scatter-Gather (SG) Mode, reading descriptors from a run-time defined memory mapped-location, or in Direct Mode, transferring data according to a descriptor stored in local registers.