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Search (47)
Compare 47 IP from 19 vendors (1 - 10)
  • Discrete Fourier Transform (DFT)
    • A fixed point bit-accurate C-Model to enable system level analysis of Xilinx DFT core.
    • Transform sizes from 12 to 1200 points with the option to change size frame by frame.
    • Less than 26 us total latency when transforming 1200 points at 245.76 MHz (using any combination of sizes)
    • Up to 18-bit two’s complement input data width, up to 18-bit two’s complement output data width with 4-bit block exponent.
  • Non-Power-of-Two FFT
    • Sample Rates: Very high clock speeds
    • FFT size: any size set of transforms (chosen at run-time) factorable into bases up to ~10
    Block Diagram -- Non-Power-of-Two FFT
  • LTE Single Carrier FFT Circuit
    • High Throughput: obtained from high clock rates (>400MHz using 65nm technology) and novel algorithms
    Block Diagram -- LTE Single Carrier FFT Circuit
  • MRDIMM DDR5 & DDR5/4 PHY & Controller
    • The DDR IP Mixed-Signal MRDIMM DDR5 PHY and DDR5/4 Combo PHY provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM or MRDIMM/ RDIMM/ LRDIMM/ UDIMM DDR5 devices
    • It is optimized for low-power and high-speed applications with robust timing and small silicon area
    • It supports all JEDEC DDR5/4 SDRAM components in the market
    Block Diagram -- MRDIMM DDR5 & DDR5/4 PHY & Controller
  • APB I2C Master/Slave Controller
    • The I2C Interface provides full support for the two-wire I2C synchronous serial interface, compatible with the ACCESS.
    • Bus physical layer, with additional support for the SMBus protocol, including Packet Error Checking (PEC).
    • Through its I2C compatibility, it provides a simple interface to a wide range of low-cost memories and I/O devices, including: EEPROMs, SRAMs, timers, A/D converters, D/A converters, clock chips, and peripheral drivers.
    Block Diagram -- APB I2C Master/Slave Controller
  • Simulation VIP for HBM
    • Speed (MHz)
    • 1800MHz (3.6 Gbps/pin)
    • Device Density
    • Supports a wide range of device densities from 1Gb to 24Gb
    Block Diagram -- Simulation VIP for HBM
  • 112G SerDes USR & XSR
    • 8 Channels per Macro, 2.5Gbps~112Gbps with TX/RX independent; NRZ Data Rate:2.5-56Gbps PAM4 Data Rates: 56-112Gbps
    • Serialization/Deserialization interface width; PCS-User interface support 64bit in PIPE
    • Two cascaded PLLs, one LC-tank based and the other ring-oscillator based
    • Digitally-control-impedance termination resistors
    Block Diagram -- 112G SerDes USR & XSR
  • MIPI C/D PHY
    • Compatible with MIPI D-PHY v1.2/CSI-2 protocol
    • Up to 4-lane 2.5Gbps/ lane
    • Support 2-Lane/4-Lane Application
    • Support HS mode (80Mbps to 2.5Gbps per lane) and LP mode (up to 10Mbps)
    Block Diagram -- MIPI C/D PHY
  • HBM2E PHY V2 - TSMC N5
    • Complete HBM2/HBM2E IP solution, including PHY, controller and verification IP, reduces integration risk while minimizing time-to-market
    • 2.5D interposer expertise and reference designs
    • Supports 2.5D-based JEDEC standard HBM2/HBM2E SDRAMs with data rates up to 3200 Mbps
    Block Diagram -- HBM2E PHY V2 - TSMC N5
  • HBM2E PHY V2 - TSMC 7FF18
    • Complete HBM2/HBM2E IP solution, including PHY, controller and verification IP, reduces integration risk while minimizing time-to-market
    • 2.5D interposer expertise and reference designs
    • Supports 2.5D-based JEDEC standard HBM2/HBM2E SDRAMs with data rates up to 3200 Mbps
    Block Diagram -- HBM2E PHY V2 - TSMC 7FF18
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