Dft IP

A fixed point bit-accurate C-Model to enable system level analysis of Xilinx DFT core.
Transform sizes from 12 to 1200 points with the option to change size frame by frame.
Less than 26 us total latency when transforming 1200 points at 245.76 MHz (using any combination of sizes)
Up to 18-bit two’s complement input data width, up to 18-bit two’s complement output data width with 4-bit block exponent.

Sample Rates: Very high clock speeds
FFT size: any size set of transforms (chosen at run-time) factorable into bases up to ~10

High Throughput: obtained from high clock rates (>400MHz using 65nm technology) and novel algorithms

The SLM SHS IP is an automated hierarchical test solution for efficiently testing SoCs or designs using multiple IP/cores, including analog/mixed-signal IP, digital logic cores and interface IP.
It significantly reduces test integration time by automatically creating a hierarchical IEEE 1500 network to access and control all IP/cores at the SoC level, and increases test quality of results (QoR), including optimizing test time and power through flexible test scheduling of IP and cores.

The SLM High-Speed Access and Test (HSAT) IP combined with the TestMAX® ALE software uses standard high speed IO interfaces such as PCIe and USB, to get test, debug and monitoring data in and out of an SoC at Gigabit data rates and avoids the need for large numbers of test and interface pins.
Test time can be reduced because the link between the test time and GPIO data rate is eliminated. Further, this solution provides a key component for Synopsys Silicon Lifecycle Management solution allowing manufacturing tests to be repeated in-system and in-field as well as providing high speed access to PVT and functional monitor dat

The DDR IP Mixed-Signal MRDIMM DDR5 PHY and DDR5/4 Combo PHY provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM or MRDIMM/ RDIMM/ LRDIMM/ UDIMM DDR5 devices
It is optimized for low-power and high-speed applications with robust timing and small silicon area
It supports all JEDEC DDR5/4 SDRAM components in the market

The I2C Interface provides full support for the two-wire I2C synchronous serial interface, compatible with the ACCESS.
Bus physical layer, with additional support for the SMBus protocol, including Packet Error Checking (PEC).
Through its I2C compatibility, it provides a simple interface to a wide range of low-cost memories and I/O devices, including: EEPROMs, SRAMs, timers, A/D converters, D/A converters, clock chips, and peripheral drivers.

8 Channels per Macro, 2.5Gbps~112Gbps with TX/RX independent; NRZ Data Rate:2.5-56Gbps PAM4 Data Rates: 56-112Gbps
Serialization/Deserialization interface width; PCS-User interface support 64bit in PIPE
Two cascaded PLLs, one LC-tank based and the other ring-oscillator based
Digitally-control-impedance termination resistors

DFT IP