DDR4 DRAM IP
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71
IP
from 5 vendors
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10)
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DDR5/DDR4/LPDDR5 Combo PHY IP - 4800Mbps (Silicon Proven in TSMC 12FFC)
- Supported DRAM type: DDR5/DDR4/LPDDR5
- Maximum controller clock frequency of 675MHz resulting in maximum DRAM data rate of 5400MT/s for DDR5
- Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 3200MT/s for DDR4
- Maximum controller clock frequency of 600MHz resulting in maximum DRAM data rate of 4800MT/s for LPDDR5?
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DDR4/ DDR3 Combo PHY IP - 2400Mbps (Silicon Proven in UMC 28HPC+)
- Supports DDR4/DDR3 SDRAM
- DDR4 JEDEC standard 1.2v I/O (POD_12 I/O)
- DDR3 JEDEC standard 1.5v I/O (SSTL_15-compatible)
- 16 bits width, Single Channel DDR4/DDR3 SDRAM Interface.
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LPDDR4/ DDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+)
- Supported DRAM type: DDR3L/DDR4/LPDDR4
- Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1866Mbps
- Interface: SSTL135/POD12/LVSTL
- Data path width scales in 32-bit increment
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DDR4/ LPDDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+)
- Supported DRAM type: DDR3L/DDR4/LPDDR4
- Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1866Mbps
- Interface: SSTL135/POD12/LVSTL
- Data path width scales in 32-bit increment
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DDR4/ LPDDR4/ DDR3L PHY IP - 3200Mbps (Silicon Proven in TSMC 12FFC)
- Supported DRAM type: DDR3L/DDR4/LPDDR4
- Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1866Mbps
- Interface: SSTL135/POD12/LVSTL
- Data path width scales in 32-bit increment
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DDR4 / DDR3/ DDR3L / LPDDR4 Memory Controller IP optimized for low latency
- Support DDR3 / DDR3L / DDR4/ 3DS DDR4/ LPDDR4 / MRAM
- Support x8/x16/x32 DRAM data bus configuration (programmable)
- Support Multi-Ranks DRAM configuration
- DDR base on DFI spec 4.0 compliant.
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DDR4/ DDR3/ DDR3L Combo PHY IP - 1600Mpbs (Silicon Proven in TSMC 28HPC+)
- Supported DRAM type: DDR3/DDR3L/DDR4
- Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1600Mbps
- Interface: SSTL15/SSTL135/POD12
- Data path width scales in 16-bit increment
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DDR3L/ LPDDR4/ DDR4 PHY IP - 1866Mbps (Silicon Proven in UMC 28HPC+)
- Supported DRAM type: DDR3L/DDR4/LPDDR4
- Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1866Mbps
- Interface: SSTL135/POD12/LVSTL
- Data path width scales in 32-bit increment
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DDR 4/3 Memory Controller IP - 2400MHz
- Support s DDR 4 /DDR3 SDRAM
- 16 bit s width , Single Channel DDR 4 /DDR3 SDRAM Interface .
- 16 bits for per channel, could support 2 x8 bits DDR3, but could not support 2 x8 bits DDR4.
- Memory Clock up to 6 66 MHz, DFI Clock up to 666 MHz .
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DDR4 Multi-modal PHY - GLOBALFOUNDRIES 12nm
- PLL-based clocking with internal clock alignment to the parallel clock on the memory controller interface
- Autonomous initialization
- Support for x72 bit channel
- Support for multiple DRAM widths (x4, x8, x16, x32)