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DDR4 DIMM Memory Model

Overview

DDR4 DIMM Memory Model provides an smart way to verify the DDR4 DIMM component of a SOC or a ASIC. The SmartDV's DDR4 DIMM memory model is fully compliant with standard DDR4 DIMM Specification and provides the following features. Better than Denali Memory Models.

DDR4 DIMM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

DDR4 DIMM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Supports DDR4 DIMM memory devices from all leading vendors.
  • Supports 100% of DDR4 DIMM protocol standard.
  • Supports DDR4 UDIMM, RDIMM and LRDIMM types.
  • Supports all the DDR4 DRAM features.
  • Supports up to 64GB device density.
  • Supports X4, X8 and X16 devices.
  • Supports all speed grades as per specification.
  • Supports ECC error detection and correction.
  • Supports Low power auto self refresh (LPASR).
  • Supports Data bus inversion (DBI).
  • Supports Single, Dual and Quad ranks.
  • Supports 16 internal banks.
  • Supports fixed burst chop (BC) of 4 and burst length (BL) of 8.
  • Supports BC4 or BL8 on-the-fly (OTF).
  • Supports Fly-by topology.
  • Supports Address Mirroring.
  • Supports Parity operations.
  • Checks for following
    • Check-points include power up initialization and power off rules
    • State based rules, Active Command rules
    • Read/Write Command rules etc.,
    • All timing violations
  • Quickly validates the implementation of the DDR4 DIMM standard.
  • Protocol checker fully compliant with DDR4 DIMM Specification.
  • Constantly monitors DDR4 DIMM behavior during simulation.
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.

Benefits

  • Faster testbench development and more complete verification of DDR4 DIMM designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

DDR4 DIMM Memory Model Block Diagram

Deliverables

  • Complete regression suite containing all the DDR4 DIMM testcases.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

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