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DDR3 memory interface controller IP

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Compare 102 IP from 19 vendors (1 - 10)
  • DDR3 SDRAM Memory Controller
    • Supports DDR3 SDRAM memory devices on AMD-Xilinx 7 Series FPGAs
    • Size optimized – ideal for low cost 7 Series FPGAs (Artix-7, Spartan-7)
    Block Diagram -- DDR3 SDRAM Memory Controller
  • DDR2 & DDR3 Fault Tolerant Memory Controller
    • Configurable to have multiple AHB ports with concurrent accesses to different memory banks
    • 96-, 64- or 32-bits interface towards SDRAM
    Block Diagram -- DDR2 & DDR3 Fault Tolerant Memory Controller
  • DDR 4/3 Memory Controller IP - 2400MHz
    • Support s DDR 4 /DDR3 SDRAM
    • 16 bit s width , Single Channel DDR 4 /DDR3 SDRAM Interface .
    • 16 bits for per channel, could support 2 x8 bits DDR3, but could not support 2 x8 bits DDR4.
    • Memory Clock up to 6 66 MHz, DFI Clock up to 666 MHz .
    Block Diagram -- DDR 4/3 Memory Controller IP - 2400MHz
  • DDR4 / DDR3/ DDR3L / LPDDR4 Memory Controller IP optimized for low latency
    • Support DDR3 / DDR3L / DDR4/ 3DS DDR4/ LPDDR4 / MRAM
    • Support x8/x16/x32 DRAM data bus configuration (programmable)
    • Support Multi-Ranks DRAM configuration
    • DDR base on DFI spec 4.0 compliant.
    Block Diagram -- DDR4 / DDR3/ DDR3L / LPDDR4 Memory Controller IP optimized for low latency
  • High Performance DDR 3/2 Memory Controller IP
    • Supports DDR3/DDR2 SDRAM
    • 16 bits width DDR2/DDR3 SDRAM Interface
    • Memory Clock up to 462MHz, DFI Clock up to 462MHz
    • Support DDR2 667/800/1066 and DDR3 667/800/1066/1333/1600/1866
  • DDR3 Controller IIP
    • Supports DDR3 protocol standard JESD79-3F Specification.
    • Compliant with DFI-version 2.0 or higher Specification.
    • Supports all the DDR3 commands as per the specs.
    • Supports up to 16 AXI ports with data width upto 512 bits.
    Block Diagram -- DDR3 Controller IIP
  • DDR3 SDRAM Controller IP with advance feautures package
    • Supports DDR3 protocol standard JESD79-3F Specification.
    • Compliant with DFI-version 2.0 or higher Specification.
    • Supports all the DDR3 commands as per the specs. Supports up to 16 AXI ports with data width upto 512 bits.
    • Supports controllable outstanding transactions for AXI write and read channels
  • DDR3 Controller
    • Maximizes bus efficiency via look-ahead command processing, bank management, auto-precharge and additive latency support
    • Latency minimized via parameterized pipelining
    • Achieves high clock rates with minimal routing constraints
    • Supports full-rate and half-rate clock operation
    • Multi-mode controller support
    Block Diagram -- DDR3 Controller
  • DDR3 Controller
    • Component support for interface width of 8 to 80 bits (RDIMM, UDIMM, and SODIMM support)
    • Controler / Phy mode or Phy only mode, plus Ping Pong Phy option
    • DDR3 (1.5V)
    • DDR3L (1.35V)
  • Universal Multi-port Memory Controller for RLDRAM2/3, DDR4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2
    • The UMMC Controller is a highly flexible and configurable design. It is targeted for high bandwidth access and low power consumption such as next generation mobile, DDR/LPDDR networking and consumer applications.
    • The controller architecture is carefully tailored to achieve reliable high-frequency operation with dynamic power management and rapid system debug capabilities.
    Block Diagram -- Universal Multi-port Memory Controller for RLDRAM2/3, DDR4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2
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Semiconductor IP