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DDR3 memory interface controller IP

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Compare 97 IP from 17 vendors (1 - 10)
  • 10Gbit/s Ethernet UDT Server for FPGAs
    • High data rate: 10Gbit/s sustained data transfer to FPGA
    • Protocol processing in Xilinx Microblaze
    • Data handling in FPGA hardware offload logic
    • Compatible with the UDT4 library
    Block Diagram -- 10Gbit/s Ethernet UDT Server for FPGAs
  • DDR4/ DDR3 Combo PHY IP - 2400Mbps (Silicon Proven in UMC 28HPC+)
    • Supports DDR4/DDR3 SDRAM
    • DDR4 JEDEC standard 1.2v I/O (POD_12 I/O)
    • DDR3 JEDEC standard 1.5v I/O (SSTL_15-compatible)
    • 16 bits width, Single Channel DDR4/DDR3 SDRAM Interface.
    Block Diagram -- DDR4/ DDR3 Combo PHY IP - 2400Mbps (Silicon Proven in UMC 28HPC+)
  • DDR3 PHY
    • Supports write leveling for each DQS group. Option to switch off write leveling for On-board memory applications
    • Supports all valid DDR3 commands
    • Supports dynamic On-Die Termination (ODT) controls
    • LatticeECP3 I/O primitives manage read skews (Read Leveling equivalent)
    Block Diagram -- DDR3 PHY
  • DO-254 AXI 7-Series DDRx (Limited) 1.00a
    • DDR3 SDRAM Features
    • Component support for interface widths up to 64 bits
    • Single rank UDIMM and SODIMM support
    • DDR3 (1.5 V) and DDR3L (1.35 V)
  • DDR3 SDRAM Memory Controller
    • Supports DDR3 SDRAM memory devices on AMD-Xilinx 7 Series FPGAs
    • Size optimized – ideal for low cost 7 Series FPGAs (Artix-7, Spartan-7)
    Block Diagram -- DDR3 SDRAM Memory Controller
  • DDR2 & DDR3 Fault Tolerant Memory Controller
    • Configurable to have multiple AHB ports with concurrent accesses to different memory banks
    • 96-, 64- or 32-bits interface towards SDRAM
    Block Diagram -- DDR2 & DDR3 Fault Tolerant Memory Controller
  • DDR3 SDRAM Controller
    • Support for all LatticeECP3 “EA” devices
    • Interfaces to Industry Standard DDR3 SDRAM components and modules compliant with JESD79-3, DDR3 SDRAM Standard
    • Interfaces to DDR3 SDRAM at speeds up to 400 MHz / 800 Mbps in -8 speed grade devices
    • Supports memory data path widths of -8, -16, -24, -32, -40, -48, -56, -64 and -72 bits
    Block Diagram -- DDR3 SDRAM Controller
  • DDR 4/3 Memory Controller IP - 2400MHz
    • Support s DDR 4 /DDR3 SDRAM
    • 16 bit s width , Single Channel DDR 4 /DDR3 SDRAM Interface .
    • 16 bits for per channel, could support 2 x8 bits DDR3, but could not support 2 x8 bits DDR4.
    • Memory Clock up to 6 66 MHz, DFI Clock up to 666 MHz .
    Block Diagram -- DDR 4/3 Memory Controller IP - 2400MHz
  • High Performance DDR 3/2 Memory Controller IP
    • Supports DDR3/DDR2 SDRAM
    • 16 bits width DDR2/DDR3 SDRAM Interface
    • Memory Clock up to 462MHz, DFI Clock up to 462MHz
    • Support DDR2 667/800/1066 and DDR3 667/800/1066/1333/1600/1866
  • DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS)
    • Four memory controller offerings: uMCTL2: multi-ported memory controller supporting JEDEC standard DDR2, DDR3, DDR4, LPDDR, LPDDR2, LPDDR3, and LPDDR4, and LPDDR4X SDRAM and DIMM modules
    • uPCTL2: Single-ported version of uMCTL2 with no internal scheduler; DDR5/4 controller: multi-ported memory controller supporting JEDEC standard DDR5, DDR4 SDRAMs and DIMM modules
    • LPDDR5/4/4X controller: multi-ported memory controller supporting JEDEC standard LPDDR5, LPDDR4, and LPDDR4X SDRAMs
    • High-bandwidth design with up to 64 CAM entries for Reads and 64 CAM entries for Writes, and latency as low as 6 clock cycles
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