DDR3 IP
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237
IP
from 33 vendors
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10)
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DDR2 & DDR3 Fault Tolerant Memory Controller
- Configurable to have multiple AHB ports with concurrent accesses to different memory banks
- 96-, 64- or 32-bits interface towards SDRAM
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DDR3 SDRAM Memory Controller
- Supports DDR3 SDRAM memory devices on AMD-Xilinx 7 Series FPGAs
- Size optimized – ideal for low cost 7 Series FPGAs (Artix-7, Spartan-7)
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Performance Enhanced version of uMCTL2 supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3 and LPDDR2 for Automotive
- Select a complete multi-ported Enhanced Universal DDR Memory Controller offering 1 to 16 host ports, or join a third-party scheduler to a single-port Enhanced Universal Protocol Controller
- Support for JEDEC standard DDR2, DDR3, DDR4, LPDDR/Mobile DDR, LPDDR2, LPDDR3, and LPDDR4 SDRAMs
- Compatible with all Synopsys DDR PHYs (excluding DDR2/DDR PHYs) using DFI-compliant interfaces
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Performance Enhanced version of DDR Enhanced Memory Ctl (uMCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
- Select a complete multi-ported Enhanced Universal DDR Memory Controller offering 1 to 16 host ports, or join a third-party scheduler to a single-port Enhanced Universal Protocol Controller
- Support for JEDEC standard DDR2, DDR3, DDR4, LPDDR/Mobile DDR, LPDDR2, LPDDR3, and LPDDR4 SDRAMs
- Compatible with all Synopsys DDR PHYs (excluding DDR2/DDR PHYs) using DFI-compliant interfaces
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DDR Enhanced Protocol Controller (uPCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
- Select a complete multi-ported Enhanced Universal DDR Memory Controller offering 1 to 16 host ports, or join a third-party scheduler to a single-port Enhanced Universal Protocol Controller
- Support for JEDEC standard DDR2, DDR3, DDR4, LPDDR/Mobile DDR, LPDDR2, LPDDR3, and LPDDR4 SDRAMs
- Compatible with all Synopsys DDR PHYs (excluding DDR2/DDR PHYs) using DFI-compliant interfaces
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high-speed interface for high-performance DDR3 PHY
- Process: TSMC 40nm LP process
- Support DDR3 1.5v
- Various ODT values provided, Res : 20~100ohm
- Various OCD values provided
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DDR3/ DDR2 Combo PHY IP - 1866Mbps (Silicon Proven in UMC 40LP)
- Supports DDR3/DDR2 SDRAM
- DDR3 JEDEC standard 1.5v I/O (SSTL_15- compatible)
- DDR2 JEDEC standard 1.8v I/O (SSTL_18- compatible)
- 16 bits width, Single Channel DDR3/DDR2 SDRAM Interface.
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DDR4 / DDR3/ DDR3L / LPDDR4 Memory Controller IP optimized for low latency
- Support DDR3 / DDR3L / DDR4/ 3DS DDR4/ LPDDR4 / MRAM
- Support x8/x16/x32 DRAM data bus configuration (programmable)
- Support Multi-Ranks DRAM configuration
- DDR base on DFI spec 4.0 compliant.
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DDR4/ DDR3 Combo PHY IP - 2400Mbps (Silicon Proven in UMC 28HPC+)
- Supports DDR4/DDR3 SDRAM
- DDR4 JEDEC standard 1.2v I/O (POD_12 I/O)
- DDR3 JEDEC standard 1.5v I/O (SSTL_15-compatible)
- 16 bits width, Single Channel DDR4/DDR3 SDRAM Interface.
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DDR4/ DDR3/ DDR3L Combo PHY IP - 1600Mpbs (Silicon Proven in TSMC 28HPC+)
- Supported DRAM type: DDR3/DDR3L/DDR4
- Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1600Mbps
- Interface: SSTL15/SSTL135/POD12
- Data path width scales in 16-bit increment
