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DDR SDRAM Controller IP

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Compare 174 IP from 23 vendors (1 - 10)
  • AMBA AHB Bus to DDR SDRAM Controller
    • External pin reduction by transferring 2 bits of data per pin.
    • Supports multiple external SDRAM banks.
    • Automatic refresh generation with programmable refresh intervals.
    • Self-refresh mode to reduce system power consumption.
    • Standard delay cells or user provided DLL for DQ and DQS alignment.
    Block Diagram -- AMBA AHB Bus to DDR SDRAM Controller
  • DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4
    • Performance of Greater than 100MHz (200 DDR)
    • Interfaces to JEDEC Standard DDR SDRAMs
    • Supports DDR SDRAM Data Widths of 16, 32 and 64 Bits
    • Supports up to 8 External Memory Banks
    Block Diagram -- DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4
  • DDR SDRAM Controller - Non-Pipelined
    • Performance of Greater than 133MHz (266 DDR)
    • Interfaces to JEDEC Standard DDR SDRAMs
    • Supports DDR SDRAM Data Widths of 16, 32 and 64 bits
    • Supports up to 8 External Memory Banks
    Block Diagram -- DDR SDRAM Controller - Non-Pipelined
  • DDR SDRAM Controller - Pipelined
    • Interfaces to industry standard DDR SDRAM devices and modules
    • High-performance DDR 400/333/266/200/133 operation for LatticeECP3, LatticeECP2/M, LatticeECP2/MS and LatticeSC/M devices; DDR 333/266/200/133 operation for LatticeECP/EC devices; and DDR 266/200/133 operation for LatticeXP devices
    • Programmable burst lengths of 2, 4 or 8 for DDR
    • Programmable CAS latency of 2 or 3 cycles for DDR
    Block Diagram -- DDR SDRAM Controller - Pipelined
  • DDR SDRAM Controller
    • Supports industry standard Double Data Rate (DDR) SDRAM.
    • Designed for ASIC and FPGA implementations in various system environments.
    • Programmable memory size and data width.
    • Supports industrial standard 64Mbit, 128Mbit and 256Mbit DDR SDRAMs.
    Block Diagram -- DDR SDRAM Controller
  • DDR and DDR2 SDRAM Controller with ALTMEMPHY Intel® FPGA IP
    • The DDR and DDR2 SDRAM Controller with ALTMEMPHY Intel FPGA Intellectual Property (IP) provides simplified interfaces to industry-standard DDR SDRAM and DDR2 SDRAM
    • The DDR and DDR2 SDRAM Controller with ALTMEMPHY Intel FPGA IP core work in conjunction with the ALTMEMPHY physical interface IP function
    • The controllers offer a half-rate interface and a full-rate interface to the customer application logic
    • For exact device support, please refer to the user guide.
    Block Diagram -- DDR and DDR2 SDRAM Controller with ALTMEMPHY Intel® FPGA IP
  • DDR and DDR2 SDRAM Controller Intel® FPGA IP Core
    • The DDR and DDR2 SDRAM controllers handle the complex aspects of using DDR and DDR2 SDRAM—initializing the memory devices, managing SDRAM banks, and keeping the devices refreshed at appropriate intervals
    • The controllers translate read-and-write requests from the local interface into all the necessary SDRAM command signals.
  • DDR3 SDRAM Controller
    • Support for all LatticeECP3 “EA” devices
    • Interfaces to Industry Standard DDR3 SDRAM components and modules compliant with JESD79-3, DDR3 SDRAM Standard
    • Interfaces to DDR3 SDRAM at speeds up to 400 MHz / 800 Mbps in -8 speed grade devices
    • Supports memory data path widths of -8, -16, -24, -32, -40, -48, -56, -64 and -72 bits
    Block Diagram -- DDR3 SDRAM Controller
  • DDR/DDR2 SDRAM Controller MACO Core
    • ispLEVER version 7.1 or later
    • MACO design kit
    • MACO license file
    Block Diagram -- DDR/DDR2 SDRAM Controller MACO Core
  • DDR3 SDRAM Controller
    • Supports industry standard Double Data Rate (DDR2 and DDR3) SDRAM.
    • Pipeline access allows continuous data bursting and hidden command execution.
    • Page hit detection supports fast column access and multiple open banks.
    • High speed implementation with standard DFI support for hard DDR PHY.
    Block Diagram -- DDR3 SDRAM Controller
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