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Cortex-M1 IP

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  • ARM 32-bit FPGA Optimized Processor
    • Designed for FPGA implementation
    • ARMv6-M instruction set architecture
    • Can run ARM7 and ARM9 Thumb subroutines
    • 3-stage, 32-bit pipeline
    Block Diagram -- ARM 32-bit FPGA Optimized Processor
  • AHB to APB Mailbox Interface
    • Simultaneously accessible from an AMBA AHB/AHB-Lite master and an AMBA 2 APB master
    • Mailbox memory storage elements made of either dual-port SRAM or FIFO blocks
    • Init/Config master interface suitable for initializing CoreABC via AHB/AHB-Lite master
    • Configurable number of interrupt flags between two processors
    Block Diagram -- AHB to APB Mailbox Interface
  • Cortex M1
    • 32-bit RISC architecture (ARMv6-M)
    • 32-bit AHB-Lite bus interface
    • Three-stage pipeline
    • 4-GB memory addressing range (the upper 0.5 GB is reserved)
  • AMBA 3.0 AHB to APB3 bridge
    • Bridges between Advanced Microcontroller Bus Architecture (AMBA) Advanced High-Performance Bus (AHB) and Advanced Peripheral Bus (APB)
    • Automatic connection to CoreAHB/CoreAHBLite and CoreAPB3 in SmartDesign
    • AMBA 3 APB compliant
    • Allows Easy Connection of APB Devices to a processor subsystem
  • low-pin-count APB component
    • Support for LPC peripheral interface (as required by the LPC specification revision 1.1)
    • I/O read/write LPC cycle types
    • Support for the KCS protocol over the LPC interface (as described in the IPMI specification v2.0)
    • Raised internal interrupt request (IRQ) on receipt of data from host controller
  • Processor Memory Aliasing
    • Facilitates remapping of Slot0 and Slot1 to facilitate processor boot
    • Flexible – Software Programmable or Set Externally
    • Ideal for Debugging a Flash-Based Subsystem
    • Very small size - uses only 15 tiles
  • External SRAM and Flash Memory Controller
    • Optimized for use with Cortex-M1 and CoreMP7
    • Two Independent Flash and SRAM AHB Ports for Separate Addressing
    • Configurable External Memory Interface
    • Interfaces to Synchronous or Asynchronous SRAM
  • FROM Memory Access Controller
    • Allows FROM access from software
    • APB bus interface
    • Small size - as small as 20 tiles
    • Easy to use
  • AMBA APB 3.0 Bus Interface
    • Implements an APB v3.0 bus fabric
    • Supports up to 16 APB slave devices
    • Auto-stitched to slave devices using SmartDesign IP design tool in Libero IDE
    • Fully compatible with Cortex-M3, Cortex-M1, Core8051s, CoreABC and other APB3 IP cores
  • AMBA APB Bus Interface
    • Implements an APB bus fabric
    • Supports up to 16 APB slave devices
    • Auto-stitched to slave devices using SmartDesign IP design tool in Libero IDE
    • Fully compatible with Cortex-M1, CoreMP7, Core8051s, CoreABC and other APB IP cores
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