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Controller IP

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Search (3,450)
Compare 3,450 IP from 200 vendors (1 - 10)
  • HYPERBUS™ Memory Controller
    • Support for HyperBus™ and xSPI standards
    • Bridges to APB, AHB, and AXI bus interfaces
    • Fully programmable SPI clock parameters
    • Automatic Slave Select control via SSCR register
    • Technology-independent HDL design
  • USB 2.0 OTG Dual Role Device (DRD) Controller
    • Compliant with OTG Supplement Rev. 1.0a
    • USB 2.0 Compliant
    • Supports 480 Mbit/s (HS), 12 Mbit/s (FS), and 1.5 Mbit/s (LS)
    • Supports Session Request Protocol (SRP) and Host Negotiation Protocol (HNP)
    Block Diagram -- USB 2.0 OTG Dual Role Device (DRD) Controller
  • UFS 2.1 Host Controller IP
    • JEDEC UFS 2.0 and UFS HCI 2.0 Compliant
    • Supports high performance M-PHY v3.0 type-1
    • 2 lanes @ 5.9 Gbps per lane
    • UniPro v1.6 link layer
    • Definable write-protect group size
    Block Diagram -- UFS 2.1 Host Controller IP
  • UFS 2.1 Device Controller IP
    • The UFS 2.1 Device controller uses an M-PHY® 3.1 Adapter Layer backed by a UniPro v1.6 Link layer controller as per the specification.
    • The UFS compliant IP cores are interface building blocks that simplify interconnect architectures in mobile platforms.
    Block Diagram -- UFS 2.1 Device Controller IP
  • SD 3.0/SDIO 3.0/eMMC 4.51 Host Controller Software Stack
    • This is a production-ready software stack for Arasan’s SD 3.0/ SDIO 3.0/ eMMC 4.51 Host Controller IP that is used to connect to SD, SDIO, or eMMC devices.
    • The SD 3.0/eMMC 4.51 stack can also be used for validating a device during its development and integration life cycles thereby helping designers to reduce the time to market for their product.
    Block Diagram -- SD 3.0/SDIO 3.0/eMMC 4.51 Host Controller Software Stack
  • SD Card Host Controller IP
    • The SD Card Host IP f is a highly integrated host controller IP solution that supports three key memory card I/O technologies:
    • The SD Card Host IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds.
    Block Diagram -- SD Card Host Controller IP
  • eMMC Host Controller IP
    • The eMMC Host controller IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds.
    • The eMMC 4.51 Host IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead.
    Block Diagram -- eMMC Host Controller IP
  • eMMC 4.51 Device Controller IP
    • Compliant to JEDEC JESD84-B45 eMMC 4.51 spec
    • Packed commands for faster processing
    • Supports cache control mechanism
    • Supports eMMC4.51 Security Protocol Commands
    Block Diagram -- eMMC 4.51 Device Controller IP
  • SD 4.1 / SDIO 4.1 / eMMC 4.51 Host Controller IP
    • The SD 4.1/SDIO 4.1 IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports three key memory card I/O technologies.
    • SD 4.1 Host Controller IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds.
    Block Diagram -- SD 4.1 / SDIO 4.1 / eMMC 4.51 Host Controller IP
  • SD 4.1 Host Controller Software Stack
    • This is a production-ready stack for Arasan’s eMMC Host Controller IP that is used to connect to SD, SDIO, or eMMC devices.
    • The SD4/SDIO4/eMMC 4.5.1 Stack can also be used for validating a device during its development and integration life cycles thereby helping designers to reduce the time to market for their product.
    Block Diagram -- SD 4.1 Host Controller Software Stack
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