ColdFire IP
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10
IP
from 2 vendors
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10)
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ColdFire V2 SPPC1 Processor Platform
- Multi-AHB crossbar switch (AXBS) connects multiple masters with various slave IP blocks
- External Bus Interface for glueless connection to external memory devices
- 10/100 Fast Ethernet Controller (FEC) with direct memory access (DMA)
- Queued serial peripheral interface (QSPI)
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ColdFire V4 SPPC1 Processor Platform
- On-board peripherals and their features include:
- FlexBus Controller
- Connects up to 6 on-chip or off-chip memories/devices
- Independently programmable transfer characteristics for each
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ColdFire V4 SPP Processor Platform
- On-board peripherals and their features include:
- FlexBus Controller
- Connects up to 6 on-chip or off-chip memories/devices
- Independently programmable transfer characteristics for each
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ColdFire V4 SPPC2 Processor Platform
- On-board peripherals and their features include:
- FlexBus Controller
- Connects up to 6 on-chip or off-chip memories/devices
- Independently programmable transfer characteristics for each
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ColdFire V1 Processor Platform
- Enhanced V1 CPU core
- Pre-integrated subsystem
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ColdFire V4 Processor
- 32-bit address and data paths
- Variable-length RISC architecture for maximum code density
- ColdFire ISA Revision C plus dedicated instructions for integrated arithmetic hardware (DIV, EMAC, and FPU)
- Branch acceleration for minimal change-of-flow execution time
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ColdFire V2 SPP5208 Processor Platform
- Multi-AHB crossbar switch (AXBS) connects multiple masters with various slave IP blocks
- External Bus Interface for glueless connection to external memory devices
- 10/100 Fast Ethernet Controller (FEC) with direct memory access (DMA)
- Queued serial peripheral interface (QSPI)
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ColdFire V1 Processor
- 32-bit processor core with 24-bit address bus
- AMBA 2 AHB unified instruction/data bus
- Single-wire debug interface
- Variable-length RISC architecture with 16, 32, and 48-bit instructions
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ColdFire V2 Processor
- Variable-length RISC, clock-multiplied core
- 166-MHz in typical 130-nm process
- Independent, decoupled pipelines: 2-stage instruction fetch pipeline (IFP); 2-stage operand execution pipeline (OEP); FIFO instruction buffer is the decoupling mechanism
- 16 user-accessible, 32-bit general purpose registers (GPRs)
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Intelligent Sensor and Power Management Design Platform
- Smart Power Subsystem
- Sensor AFE
- MCU Subsystem
