Camera processor IP

Inclusive of all Camera Link defined camera configurations including the proposed 80 bit extensions which utilize one to three Channel Link or equivalent devices.
Supports single camera or two independent base cameras for multi-view or 3D stereo applications.
Fully synchronous pipeline architecture supports high speed implementation in low cost logic devices.
Dynamic reconfiguration of the processing chain via register interface in addition to a user selected default setup.

provides pixel processing functions such as cropping, color space conversion (CSC), alpha blending, 3D LUT, and flexible resizing.
Support input data of various compressed or uncompressed RGB and YUV formats. After being processed by the pixel processor, the data can be output in uncompressed, compressed, or normalized formats.

32bit DVP interface, 24bit ISP pipeline
Dual pixel per cycle throughput
Wide Dynamic Range Tone Mapping (WDR)
Multi-exposure HDR (Native/build in HDR, Compand output, DOL/Stagger, Stagger output)

Supports DVP Input Interface
Input color formats: 8-bit, 10-bit, 12-bit Bayer; 8-bit, 10-bit YUV BT.601, BT.656; 8-bit, 10-bit monochrome
SW Register Configuration: 32-bit AHB Slave
Frame rate control, configurable output FPS range from 60fps to 1fps

Multi-sensor interface with up to 20-bit linear video input
Up to 8 independent camera sources of max resolution 48 Megapixels / 8K (8192 x 6144)

Camera Processor IP