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Alphawave Semi IP

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Compare 984 IP from 84 vendors (1 - 10)
  • Specialed 20V Analog I/O in TSMC 55nm
    • A TSMC 55nm LP Specialized 20V Analog I/O in Standard Low Voltage CMOS
    • This silicon-proven TSMC 55nm LP 20V ESD cell is a high-voltage electrostatic discharge (ESD) protection solution specifically engineered forlow-power and high-performance applications.
    • This ESD cellis designed to safeguard high- voltage interfaces commonly found in analog, mixed-signal, RF, and power management ICs, where protection against electrostatic discharge events is critical for long-term reliability.
  • ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
    • A Wirebond and FlipChip compatible <80fF ESD Solutions for Multi-Gigabit SerDes Applications.
    • This silicon-proven TSMC 28nm Digital I/O Library delivers a low-capacitance, high-reliability interface solution optimized for advanced semiconductor applications.
    • Featuring low-capacitance LVDS differential pairs (<250fF per pin) at 0.8V, this library ensures superior signal integrity for high-speed applications.
    Block Diagram -- ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
  • UCIe based 8-bit 48-Gsps Transceiver (ADC/DAC/PLL/UCIe)
    • 48-Gsps peak sample rate
    • 8 bit resolution
    • UCIe SP (16x lanes at 16Gbps) with streaming controller
  • UCIe based 12-bit 12-Gsps Transceiver (ADC/DAC/PLL/UCIe)
    • 12-Gsps peak sample rate
    • 12 bit resolution (programmable)
    • UCIe SP (16x lanes at 16Gbps) with streaming controller
  • Fully-coherent RISC-V Tensor Unit
    • The bulk of computations in Large Language Models (LLMs) is in fully-connected layers that can be efficiently implemented as matrix multiplication.
    • The Tensor Unit provides hardware specifically tailored to matrix multiplication workloads, resulting in a huge performance boost for AI without a big power consumption.
    Block Diagram -- Fully-coherent RISC-V Tensor Unit
  • Fully-custom RISC-V Vector Unit
    • A Vector Unit is composed of several "Vector Cores", roughly equivalent to a GPU Core, that perform multiple calculations in parallel.
    • Each Vector Core has arithmetic units capable of performing addition, subtraction, fused multiply-add, division, square root, and logic operations.
    Block Diagram -- Fully-custom RISC-V Vector Unit
  • 64-bit Out-of-Order RISC-V Customisable IP Core
    • Ready for the most demanding workloads, Atrevido supports large memory capacities with its 64-bit native data path. With its complete MMU support, Atrevido is also Linux-ready, including multiprocessing.
    Block Diagram -- 64-bit Out-of-Order RISC-V Customisable IP Core
  • 10Gb Ethernet PCS
    • Complete 10Gb Ethernet Physical Coding Sublayer (PCS) Solution Based on the ORCA 10 Gbits/s Line Interface (ORLI10G) FPSC, Enabling Flexible10GbE LAN/WAN Application Solutions.
    • IP Targeted to the ORLI10G Programmable Array Section Implements Functionality Conforming to IEEE Standard 802.3ae, Including:
    • ORCA Bitstream Format Allows Direct Downloading and Turnkey Functionality.
    • ModelSim Simulation Models and Test Benches Available for Free Evaluation.
    Block Diagram -- 10Gb Ethernet PCS
  • Wide-Range Low-Area Digital PLL in TSMC 28HPM
    • TSMC 28HPM
    • Wide Range: 40kHz to 4 GHz
    • Size: <0.0mm2
    Block Diagram -- Wide-Range Low-Area Digital PLL in TSMC 28HPM
  • NFC Semiconductor IP - Combo (digital & analog)
    • Process: 180nm TSMC or 65nm TSMC(Test version)
    • Diesize(incl. pads): 3,000 x 3,000
    • Power Consumption: 20 uA(sleep mode), 80mA(active mode)
    • CPU: 8051
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Semiconductor IP