IP Catalog > ARINC 429

ARINC 429 IP

Filter
Filter

Login required.

Sign in

Search (16)
Compare 16 IP from 10 vendors (1 - 10)
  • ARINC 429 Verification IP
    • Supports ARINC SPECIFICATION 429 PART 1-17.
    • Supports all word structures and protocol necessary to establish bus communication as per the specs.
    • Supports simplex, twisted shielded pair data bus standard Mark 33 Digital Information Transfer System bus.
    • Supports LRU with multiple transmitters and receivers communicating on different buses.
    Block Diagram -- ARINC 429 Verification IP
  • ARINC 429 Synthesizable Transactor
    • Supports ARINC SPECIFICATION 429 PART 1-17
    • Supports all word structures and protocol necessary to establish bus communication as per the specs
    • Supports simplex, twisted shielded pair data bus standard Mark 33 Digital Information Transfer System bus
    • Supports LRU with multiple transmitters and receivers communicating on different buses
    Block Diagram -- ARINC 429 Synthesizable Transactor
  • ARINC 429 IP Core
    • Implements ARINC 429 Data Bus Communication Protocol.
    • Supports both Transmit and Receive functionality for ARINC 429 words.
    • Configurable data rates for flexible integration into avionics systems.
    • Provides advanced error detection mechanisms for high data integrity.
    • Bare-metal application or PetaLinux OS with associated APIs.
    Block Diagram -- ARINC 429 IP Core
  • ARINC 429 IP Core
    • Supports ARINC 429 Specification
    • Configurable up to 32 Rx and 16 Tx Channels
    • Supports 12.5 kbit/s and 100kbit/s data rates
    Block Diagram -- ARINC 429 IP Core
  • ARINC 429 IP-Core with DO-254 Package
    • Applicable Standards:
    • Configuration support per channel:
    • Technical features:
    • Supported tools:
    Block Diagram -- ARINC 429 IP-Core with DO-254 Package
  • ARINC 429 IP Core
    • Multichannel module supporting ARINC429 Receiver/Transmitter.
    • Configurable module supporting any number of receivers and transmitters (Standard with 16 receivers & 8 transmitters).
    • Configurable data rate supporting from 12.5 Kbps to 1 Mbps.
    • Parity & Gap generators & checkers for high data integrity.
    Block Diagram -- ARINC 429 IP Core
  • ARINC 429 Tx & Rx
    • User ARINC 429 configuration
    • Programmable data rate for 100 kbsor 12.5kbs
    • Transmitter and Receiver can b eEnabled /Disabled
    • Based on vendor and technology independent VHDL code
  • ARINC 429 Synchronous Transmitter Receiver
    • 1 Independent Receivers (Rx) with FIFO
    • 1 Independent Transmitter (Tx) with FIFO
    • Decoding signals interface type
    • 16-Bit Data-bus
  • ARINC 708A Verification IP
    • Available in Verilog, System Verilog, and UVM.
    • Control Word information can be user-configurable / Random. (Protected By parity).
    • Data word header will be according to the 270 271 label Frame received from Control Word.
    • Support for Hazards, Faults, and Errors.
    Block Diagram -- ARINC 708A Verification IP
  • ARINC 708A Verification IP
    • Available in Verilog, System Verilog, and UVM.
    • Control Word information can be user-configurable / Random. (Protected By parity).
    • Data word header will be according to the 270 271 label Frame received from Control Word.
    • Support for Hazards, Faults, and Errors.
    Block Diagram -- ARINC 708A Verification IP
×
Semiconductor IP