ARINC 429 IP Core implements ARINC 429 standard. IP Core contains Rx and Tx processing blocks, Controller Block, Internal Memory and External Memory Interfaces. A429 IP communicates with CPU (Central Processing Unit) and external memory through AXI interface.
IP Core uses AXI interface as internal local bus. AXI interface is 32-bit data bus which has 32-bit addressing, 32-bit read and write channel. IP supports to 32 receive channel number and
16 transmit channel number.
The IP is designed to be compatible with DO-254. ARINC 429 IP is field approved.
ARINC 429 IP Core
Overview
Key Features
- Supports ARINC 429 Specification
- Configurable up to 32 Rx and 16 Tx Channels
- Supports 12.5 kbit/s and 100kbit/s data rates
- Contains 32-bit local data bus
- Contains Individual and Circular buffer area which have 1024 word depth for each channel
- Supports single and periodic data transfer
- Filter mechanism based on SDI, ESSM, Label of ARINC 429 data
- Occuring of filter process in FPGA
- Communication with CPU and external memory
- Field Approved
- DO-254 compliant
Block Diagram
Deliverables
- Encrypted VHDL source code
- ARINC 429 IP Core User Guide
- Optional DO-254 Certification Data Package is available.
Technical Specifications
Related IPs
- ARINC 818-3 IP Core
- ARINC818 controller Transmitter and Receiver IP core
- ARINC 429 Bus Interface
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core
- ARINC 429 Synchronous Transmitter Receiver
- BCH Encoder/Decoder IP Core