Amba chi IP

Compare 133 IP from 37 vendors (1 - 10)

Simulation VIP for AMBA CHI
- Transaction type
- Monitoring and driving of all protocol Opcodes
- Dummy interconnect
- Dummy CHI-based interconnect support. When interconnect is not present, the Active Hn-F can generate snoop requests and respond to Rn-F commands
AMBA 5 CHI Verification IP
- VIP is Compliant with the latest ARM™ AMBA5 CHI.
- Support any type of network topology like Crossbar, Ring, Mesh, etc…
- Support for all types of AMBA5 CHI Nodes:
  - Requester (RN-F, RN-D, RN-I)
  - Home (HN-F, HN-I)
  - Subordinate (SN-F, SN-I)
- Requester (RN-F, RN-D, RN-I)
AMBA 5 CHI Verification IP
- Compliant with the latest ARM AMBA 5 CHI specification (CHI-D).
- Supports CHI Master, Slave, Interconnect, Monitor and Checker.
- Support for Protocol, Network and Link layer communication, including flow control mechanisms across RN2HN and HN2SN links.
- Supports all CHI protocol node types:
AMBA 5 CHI Synthesizable Transactor
- Compliant with the latest ARM AMBA 5 CHI specification (CHI-B).
- Supports CHI Master, Slave, Interconnect.
- Support for Protocol, Network and Link layer communication, including flow control mechanisms across RN2HN and HN2SN links.
- Supports all CHI protocol node types:
AMBA 5 CHI Assertion IP
- Specification Compliance
- Compliant with the latest ARM AMBA 5 CHI specification.
- Supports all ARM AMBA 5 CHI data widths.
- Supports for Protocol, Network and Link layer communication, including flow control mechanisms across RN2HN and HN2SN links.
AMBA 5 CHI Verification IP
- VIP is Compliant with the latest ARM™ AMBA5 CHI.
- Support any type of network topology like Crossbar, Ring, Mesh, etc…
- Support for all types of AMBA5 CHI Nodes:
  - Requester (RN-F, RN-D, RN-I)
  - Home (HN-F, HN-I)
  - Subordinate (SN-F, SN-I)
- Requester (RN-F, RN-D, RN-I)
Simulation VIP for AMBA ATP
- Definition of Adaptive Traffic Profiles
- Definition of write and read traffic profiles using the ATP specification terminology
- Timing Control
- Support of primary and secondary timing parameters
DDR Controller supporting DDR5 with a CHI interface and Advanced Feature Package
- Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
- Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
- DFI 5.0 compliant interface to Synopsys DDR5/4 PHY or other DDR5/4 PHYs
- Best in class performance with unique features such as QoS-based scheduling and phase-aware scheduling
DDR Controller supporting DDR5 and DDR4 with a CHI interface and Advanced Feature Package
- Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
- Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
- DFI 5.0 compliant interface to Synopsys DDR5/4 PHY or other DDR5/4 PHYs
- Best in class performance with unique features such as QoS-based scheduling and phase-aware scheduling
DDR Controller supporting DDR5 and DDR4 with a CHI interface
- Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
- Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
- DFI 5.0 compliant interface to Synopsys DDR5/4 PHY or other DDR5/4 PHYs
- Best in class performance with unique features such as QoS-based scheduling and phase-aware scheduling

AMBA CHI IP