IP Catalog > AMBA CHI

AMBA CHI IP

Filter
Filter

Login required.

Sign in

Login required.

Sign in

Search (107)
Compare 107 IP from 34 vendors (1 - 10)
  • DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS)
    • Four memory controller offerings: uMCTL2: multi-ported memory controller supporting JEDEC standard DDR2, DDR3, DDR4, LPDDR, LPDDR2, LPDDR3, and LPDDR4, and LPDDR4X SDRAM and DIMM modules
    • uPCTL2: Single-ported version of uMCTL2 with no internal scheduler; DDR5/4 controller: multi-ported memory controller supporting JEDEC standard DDR5, DDR4 SDRAMs and DIMM modules
    • LPDDR5/4/4X controller: multi-ported memory controller supporting JEDEC standard LPDDR5, LPDDR4, and LPDDR4X SDRAMs
    • High-bandwidth design with up to 64 CAM entries for Reads and 64 CAM entries for Writes, and latency as low as 6 clock cycles
  • DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS) targeting automotive
    • Four memory controller offerings: uMCTL2: multi-ported memory controller supporting JEDEC standard DDR2, DDR3, DDR4, LPDDR, LPDDR2, LPDDR3, and LPDDR4, and LPDDR4X SDRAM and DIMM modules
    • uPCTL2: Single-ported version of uMCTL2 with no internal scheduler; DDR5/4 controller: multi-ported memory controller supporting JEDEC standard DDR5, DDR4 SDRAMs and DIMM modules
    • LPDDR5/4/4X controller: multi-ported memory controller supporting JEDEC standard LPDDR5, LPDDR4, and LPDDR4X SDRAMs
    • High-bandwidth design with up to 64 CAM entries for Reads and 64 CAM entries for Writes, and latency as low as 6 clock cycles
  • Tessent NoC Monitor
    • Full transaction and trace-level visibility of traffic
    • Wide range of measurements, analytics statistics: transactions, bus cycles, latency, duration, beats, concurrency
    Block Diagram -- Tessent NoC Monitor
  • Coherent Mesh Network
    • High-Performance, Scalable Coherent Mesh
    • Reduce SoC Integration Time
    • Maximize Compute Density
    • Coherent Multichip Links
  • UCIe-S PHY for Standard Package (x16) in TSMC N6, North/South Orientation
    • Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
    • Compliant with the latest UCIe specification
    • Integrated signal integrity monitors and comprehensive test and repair features
    • Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
    Block Diagram -- UCIe-S PHY for Standard Package (x16) in TSMC N6, North/South Orientation
  • UCIe-S PHY for Standard Package (x16) in TSMC N5A, N/S, for Automotive, ASIL B Random, AEC-Q100 Grade 2
    • Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
    • Compliant with the latest UCIe specification
    • Integrated signal integrity monitors and comprehensive test and repair features
    • Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
    Block Diagram -- UCIe-S PHY for Standard Package (x16) in TSMC N5A, N/S, for Automotive, ASIL B Random, AEC-Q100 Grade 2
  • UCIe-S PHY for Standard Package (x16) in TSMC N5, North/South Orientation
    • Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
    • Compliant with the latest UCIe specification
    • Integrated signal integrity monitors and comprehensive test and repair features
    • Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
    Block Diagram -- UCIe-S PHY for Standard Package (x16) in TSMC N5, North/South Orientation
  • UCIe-A PHY for Advanced Package (x64) in TSMC N5, North/South Orientation
    • Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
    • Compliant with the latest UCIe specification
    • Integrated signal integrity monitors and comprehensive test and repair features
    • Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
    Block Diagram -- UCIe-A PHY for Advanced Package (x64) in TSMC N5, North/South Orientation
  • UCIe-A PHY for Advanced Package (x64) in TSMC N5, East/West Orientation with 8collumn module configuration
    • Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
    • Compliant with the latest UCIe specification
    • Integrated signal integrity monitors and comprehensive test and repair features
    • Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
    Block Diagram -- UCIe-A PHY for Advanced Package (x64) in TSMC N5, East/West Orientation with 8collumn module configuration
  • UCIe-S PHY for Standard Package (x16) in TSMC N4P, North/South Orientation
    • Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
    • Compliant with the latest UCIe specification
    • Integrated signal integrity monitors and comprehensive test and repair features
    • Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
    Block Diagram -- UCIe-S PHY for Standard Package (x16) in TSMC N4P, North/South Orientation
×
Semiconductor IP