7nm 58G DSP-based PAM4/NRZ SerDes IP
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156
IP
from 26 vendors
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10)
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12 bit 250MSPS ADC on TSMC 7nm
- TSMC 7nm
- Ultra high-performance low-power ADC
- Integrated input buffer
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12-bit, 8-GSPS DAC Ultra Low Power on 7nm
- 7nm FinFet
- 12-bit resolution
- 8-GSPS update rate
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12-bit, 8 GSPS ADC in 7nm CMOS
- 7nm FinFet
- Ultra high-performance low-power ADC
- 12-bit ADC resolution
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PHY for PCIe 5.0 and CXL for TSMC 7nm FinFet
- High-performance PHY for data center applications
- Low-latency, long-reach, and low-power modes
- Wide range of protocols that support networking, storage, and computing applications
- Multi-protocol support for application flexibility
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112G-XSR Pam4 for TSMC 7nm FinFET CMOS
- TSMC 7nm FinFET CMOS Process
- 112G PAM4 interface compatible to LR and VSR
- Eight-lane compact footprint for high-density designs
- Integrated BIST capable of producing and checking PRBS
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MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 7 FF
- Compliant with MIPI D-PHY spec up to v2.5 and C-PHY spec up to v2.0
- Support both MIPI DSI and CSI-2 protocols
- Support HS data rate up to 6Gbps ( 6Gsps ) per lane (per trio)
- Support LS data rate of 10Mbps and Ultra-low power mode
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MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 7 FF
- Compliant with MIPI D-PHY spec up to v2.5 and C-PHY spec up to v2.0
- Support both MIPI DSI and CSI-2 protocols
- Support HS data rate up to 6Gbps ( 6Gsps ) per lane (per trio)
- Support LS data rate of 10Mbps and Ultra-low power mode
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PVT - Process, Voltage, and Temperature Monitor TSMC 7nm
- ± 4C temperature accuracy without trim
- ± 1C temperature accuracy after single room temperature trim
- 0.011C temperature resolution
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PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 7nm
- Compatible with PCIe base Specification
- Full compatible with PIPE4.2 interface specification
- Independent channel power down control
- Implemented Receiver equalization Adaptive-CTLE to compensate insertion loss
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LPDDR5X/5/4X/4 combo PHY at 7nm
- Unbeatable performance-driven and low-power-driven PPA
- Ultra-low read/write latency with programmable PHY boundary timing
- Channel equalization with FFE and DFE
