5g nr ldpc IP

The 5G NR LDPC Decoder IP Core offers a robust solution for LDPC decoding, featuring a dedicated LDPC decoder block for optimal performance.
It employs the Min-Sum LDPC decoding algorithm to ensure efficient decoding.
The core allows for programmable internal bit widths at compile time, though the default values are usually sufficient.

The LDPC decoder product suite has been specifically designed as flexible IP to address the unique challenges of 5G NR across all use cases covered by the current standards, deliver market leading performance and efficiency, and be easily integrated into designs.

Low-density parity-check (LDPC) codes are linear error correcting codes that help you to transmit and receive messages over noisy channels
The 5G LDPC and LDPC-V Intel® FPGA IP implement LDPC codes compliant with the 3rd Generation Partnership Project (3GPP) 5G specification for integration in your wireless design.
LDPC codes offer better spectral efficiency than Turbo codes and support the high throughput for 5G new radio (NR).

Complete implementation of the relevant 3GPP standards
Improved spectral efficiency across low SINR range against industry-standard simulation toolbox

The PDSCH Encoder and PUSCH Decoder products simplify the creation of high performance 5G NR implementations.
PDSCH Encoder features the new QAM mapper and Scrambler functionality. These are integrated with LDPC encoder chain and transport block chain components.
PDSCH encoder has a configurable IQ parallelism for improved performance per clock.
The functions included are CRC, Segmentation, LDPC encode, Rate matching, Integrated HARQ, Concatenation, Scrambling and Modulation.

Low-density parity-check (LDPC) codes are linear error correction codes that allow you to transmit messages over noisy channels.
Intel's 5G Low-Density Parity Check (LDPC) Intel FPGA Intellectual Property (IP) core is a high-throughput encoder or decoder that is compliant with 3rd Generation Partnership Project (3GPP) 5G specification.

5G NR LDPC IP