5g nr IP

Comprehensive Support: All PRACH formats and configuration indexes described in 3GPP 38.211 are fully supported.
Versatile Sequences: Length-139 and length-839 sequences are included.
Frequency Multiplexing: Capable of decoding up to 8 frequencies multiplexed PRACHs.

The 5G NR LDPC Decoder IP Core offers a robust solution for LDPC decoding, featuring a dedicated LDPC decoder block for optimal performance.
It employs the Min-Sum LDPC decoding algorithm to ensure efficient decoding.
The core allows for programmable internal bit widths at compile time, though the default values are usually sufficient.

The Forward Error Correction (FEC) sub-system is one of the essential basing blocks in any communication systems so a powerful FEC code is needed.
The New Radio (NR) FEC for the control channel is proposed to be designed based on Polar codes allowing close to the Shannon limit/Capacity operation.
The Polar code successive cancellation decoding process as needed for 3GPP physical layer standard.

Complete implementation of the relevant 3GPP standards
Improved spectral efficiency across low SINR range against industry-standard simulation toolbox

The PDSCH Encoder and PUSCH Decoder products simplify the creation of high performance 5G NR implementations.
PDSCH Encoder features the new QAM mapper and Scrambler functionality. These are integrated with LDPC encoder chain and transport block chain components.
PDSCH encoder has a configurable IQ parallelism for improved performance per clock.
The functions included are CRC, Segmentation, LDPC encode, Rate matching, Integrated HARQ, Concatenation, Scrambling and Modulation.

The patented polar encoding and decoding IP for the 3GPP New Radio uplink and downlink includes the entire processing chain, to provide quick and easy integration and minimize the amount of extra work needed.
The polar core uses PC- and CRC-aided SCL polar decoding techniques, in order to achieve compromise-free error correction performance.

The LDPC decoder product suite has been specifically designed as flexible IP to address the unique challenges of 5G NR across all use cases covered by the current standards, deliver market leading performance and efficiency, and be easily integrated into designs.

The 5G Polar Intel® FPGA IP implements a forward error correction (FEC) encoder and decoder based on polar codes compliant with the 3rd Generation Partnership Project (3GPP) 5G specification for integration into your wireless design
Polar codes represent an emerging class of error correction supporting the high throughput requirements for 5G new radio (NR).

Low-density parity-check (LDPC) codes are linear error correcting codes that help you to transmit and receive messages over noisy channels
The 5G LDPC and LDPC-V Intel® FPGA IP implement LDPC codes compliant with the 3rd Generation Partnership Project (3GPP) 5G specification for integration in your wireless design.
LDPC codes offer better spectral efficiency than Turbo codes and support the high throughput for 5G new radio (NR).

5G NR IP