40nm ULP Memory IP
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8
IP
from 5 vendors
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8)
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FTP Non Volatile Memory for Standard TSMC 40nm ULP Process
- Ultra Low Power Read (30uA/MHz for 39b-IO) at 0.85V Single Power
- 10-Time Programmable
- > 10 years retention
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4Kx32 Bits OTP (One-Time Programmable) IP, TSMC 40nm ULP 1.1V/2.5V Process
- Fully compatible with standard TSMC 40nm ULP 1.1V/2.5V CMOS logic process
- Low voltage: 1.1V+/-10% read and 2.65V+/-5% program
- High-speed program: 10us single-bit programming and up to 4-bit programming
- High-speed read: 25Mhz read clock (40ns cycle time) per 32-bit word
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4608x12 Bits OTP (One-Time Programmable) IP, TSMC 40ULP 0.9V/2.5V Process
- Fully compatible with standard TSMC 40nm ULP 0.9V/2.5V CMOS logic process
- Low voltage: VDD 0.9 V ± 10% for read and program; VDDP: 1.71–3.60 V for read and 2.65 V ± 5% for program
- High speed program: 10-us programming time and support up to dual-bit concurrent programming at one CLK cycle
- High speed read: 10-MHz read clock (100-ns cycle time) per 12-bit word.
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1Kx8 Bits OTP (One-Time Programmable) IP, TSMC 40ULP 1.1/2.5V Process
- Fully compatible with standard TSMC 40nm ULP 1.1V / 2.5V CMOS process
- Low voltage: VDD 1.1 V ± 10% read and VDDP 2.1 V ± 5% program
- High speed program: 10-us single-bit programming
- High speed read: 9-MHz read clock at 8-bit word.
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Bulk 40ULP Single Port SRAM with low power retention mode, high speed pins on 1 side
- Ultra low power data retention. Memory instances generated by the Bulk 40 ULPgo into a deep sleep mode that retains data at minimal power consumption.
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SDRAM DDR4/3/2 & LPDDR4/3/2 Hardened PHY - TSMC 40nm ULP
- + DDR4/DDR3/DDR2 PHY IP fully compliant with the DFI 4.0 Specification
- + LPDDR4/LPDDR3/LPDDR2 PHY IP fully compliant with the DFI 4.0 Specification.
- + Support speeds up to 2133Mbps with 1.8V oxide and 1600Mbps with 2.5V Oxide.
- + IP is split into 2 hard macros.