2D IP
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143
IP
from 45 vendors
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10)
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2D Graphics Hardware Accelerator (AHB Bus)
- Generates bitmaps from graphics instructions as well as combining existing bitmaps on and off-screen using one of 256 Raster Operations. A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT) which lay the foundation for power hardware graphics primitive operations
- Generates characters from compressed bitmaps using its FONT Bitmap Color Expansion Unit
- Performs Alpha Blend operations of bitmaps with its Alpha Blend unit
- Draws lines, polygons, circles using its hardware efficient & pixel accurate Bresenham Algorithm Line Drawing Unit
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2D Graphics Hardware Accelerator (AXI Bus)
- Generates bitmaps from graphics instructions as well as combining existing bitmaps on and off-screen using one of 256 Raster Operations. A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT) which lay the foundation for power hardware graphics primitive operations
- Generates characters from compressed bitmaps using its FONT Bitmap Color Expansion Unit
- Performs Alpha Blend operations of bitmaps with its Alpha Blend unit
- Draws lines, polygons, circles using its hardware efficient & pixel accurate Bresenham Algorithm Line Drawing Unit
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2D GPU IP Core - Target Display Resolution: 8K
- Xwindow (EXA)
- Hardware Composer (HWC)
- DirectFB
- Pixel Rate (Pixels/Cycle): 4
- Target Display Resolution: 8K
- Direct 3D Tile Status and Buffer Option: yes
- Formats Support: RGB & YUV FP16/32
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2D GPU IP Core - Target Display Resolution: 4K
- Xwindow (EXA)
- Hardware Composer (HWC)
- DirectFB
- Pixel Rate (Pixels/Cycle): 2
- Target Display Resolution: 4K
- Direct 3D Tile Status and Buffer Option: yes
- Formats Support: RGB & YUV FP16/32
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2D GPU IP Core - Target Display Resolution: 2.5K~4K
- Xwindow (EXA)
- Hardware Composer (HWC)
- DirectFB
- Pixel Rate (Pixels/Cycle): 4
- Target Display Resolution: 2.5K~4K
- Direct 3D Tile Status and Buffer Option: yes
- Formats Support: RGB & YUV Limited
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Advanced 2D Noise Reduction core
- 2D noise reduction filter
- Advanced new noise reduction algorithm
- Adjust the logic size and performance of core by changing the parameter of RTL source code level
- Noise filtering in Bayer/YUV/RGB domain
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2D Blit and Raster Graphics
- All buffer formats 100% compatible
- Flexible pixel formats (1/2/4/8/16/18/24/32 bpp; any bit width per channel)
- YUV support (packed, planar, 4:4:4, 4:2:2, 4:2:0, progressive, interlaced)
- Dynamic re-configuration of processing units
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2D Scaler
- Support for multi-color plane (RGB and YCbCr4:4:4), serial filtering
- Dynamic input and output frame size updating
- Supports multi-scaling algorithms
- Configurable number of filter taps for Lanczos coefficient set
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Advanced 2D Graphics Controller
- Fully synchronous, synthesizable and technology independent RTL code
- Capable of drawing shapes such as pixels, lines and rectangles
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High-performance and low-power 2D vector graphics IP core
- K3000 is an OpenVG 1.1 compliant 2D vector graphics IP core that achieves the industry’s highest-level PPA (Power / Performance / Area), realizing smooth 2D vector drawing in combination with Qt and various font engines compliant with OpenVG 1.1.