1394b IP
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7
IP
from 2 vendors
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7)
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Hardware Offload Engine for 1394b AS5643
- AS5643 compliant interface with hardware based STOF offload
- Hardware DMA engines with message label mapped buffers
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GP2Lynx Layer IP Core for 1394b
- AS5643 compliant interface with hardware based STOF offload
- Supports S100 / S200 / S400 / S800 / S1600 / S3200 data rates
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OHCI Layer IP Core for 1394b
- AS5643 compliant interface with hardware based STOF offload
- Supports S100 / S200 / S400 / S800 / S1600 / S3200 data rates
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PHY Layer IP Core for 1394b
- AS5643 compliant interface
- Supports S100 / S200 / S400 / S800 / S1600 / S3200 data rates
- Complete PHY layer implementation
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1394B I/O
- Single-chip solution: The PHY IP can be combined with Link Layer IPs, creating smaller solutions. Additional components can be added to create a System On Chip (SOC) solution.
- Flexible number of ports: Commercially available PHY chips have a fixed number of ports which for small peripherals is often overkill. On the other hand, host adapter would likely benefit from 3 or more ports and a hub could even have more than that. For a PHY based on FPGA technology, the user can customize the number of ports as required.
- Optional debug and test features: Optionally the user can include debug and test features like BERT (Bit Error Rate Test) Low level data monitoring and recording
- Field-upgradable: The used FPGAs are field upgradable thus allowing the addition new features or bug fixes, even if the device is already in the field.
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1394b FPGA Link Layer Controller
- Complete IP solution combining FireLink® Basic and FireGate
- IEEE-1394-2008 Beta
- Supports S100-S3200 transfer rates
- Minimal Footprint
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FireLink IEEE1394b Link Layer Controller
- IEEE 1394-1995, 1394a-2000 and 1394b-2002 compliant
- Supports 100, 200, 400, and 800Mbps data transfer rates
- Supports Legacy and Beta packets RX/TX (depending on the connected PHY)
- Supports all standard 1394 packet types