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10 100 1000M Ethernet PHY IP

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Compare 10 IP from 7 vendors (1 - 10)
  • GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in SAM 14LPP
    • EEE 802.3-2008, IEEE 802.3az fully standards compliant
    • IEEE 1588-2008 support
    • BroadR-Reach™ support
    • Dual port MAC interface:
    Block Diagram -- GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in SAM 14LPP
  • Simulation VIP for Ethernet Base-T1
    • 10 Base-T1s Interface
    • Based on IEEE 802.3cg-2019 (Clause 147)
    • 4b/5b Encoder/Decoder
    • 17bit self-synchronizing scrambler/descrambler
    Block Diagram -- Simulation VIP for Ethernet Base-T1
  • DO-254 10/100/1000 Ethernet MAC
    • Configurable bit rate (1000 Mb/s, 100 Mb/s or 10 Mb/s)
    • DAL A according to DO-254 / ED-80
    • Compliant to the following clauses of the IEEE 802.3-2008 specification:
    • Compliant to the RMII specification (March 20, 1998)
    Block Diagram -- DO-254 10/100/1000 Ethernet MAC
  • Low-Latency 10/100/1000 Ethernet MAC
    • The LLEMAC-1G implements an Ethernet Media Access Controller (MAC) compatible with the 10/100 Mbps IEEE 802.3 and 1Gbps IEEE 802.3-2002 specifications.
    • Featuring extremely low egress and ingress latency, the core is ideal for the implementation of TSN Ethernet nodes, live streaming and other devices requiring minimum latency in the reception and transition of Ethernet frames.  
    Block Diagram -- Low-Latency 10/100/1000 Ethernet MAC
  • MAC 10/100/1000 Ethernet Controller
    • IEEE 802.3-2002 specification with preamble, start-of-frame delimiter (SFD), frame padding generation and cyclic redundancy code (CRC) generation and checking is fully implemented
    • Supports 10/100 Mbps or 1000 Mbps operation (selectable via a core configuration registers)
    • Supports full- and half-duplex operation (selectable via a core configuration registers)
    • CSMA/CD protocol for half-duplex operation
    Block Diagram -- MAC 10/100/1000 Ethernet Controller
  • Tri-Mode Ethernet Media Access Controller (TEMAC)
    • Designed to IEEE 802.3-2012 specification
    • Supports 10/100/1000/2500 Mbps Ethernet
    • Configurable half-duplex and full-duplex operation
    • Configured and monitored through an optional independent microprocessor-neutral interface
  • Ethernet 1G/2.5G BASE-X PCS/PMA or SGMII
    • Designed to IEEE 802.3-2012 specification
    • Full-duplex operation
    • Supports speeds up to 2.5 Gigabit per second
    • Supports Select I/O or Transceiver implementations
  • Serial Gigabit Media Independent Interface
    • Offers a reduced pin-count interface between MII or GMII Ethernet MACs and Physical Layer devices
    • Supports Revision 1.7 of the Serial GMII specification
    • Supports MII 10/100 Mbps and GMII 1000 Mbps Ethernet speeds
    • Supports Full Duplex transfers at all speeds, and Half Duplex at 10/100Mbps
  • XPS_LL_TEMAC
    • Independent 2K, 4K, 8K, 16K, or 32K Byte TX and RX data FIFOs for queueing frames
    • Filtering of "bad" receive frames
    • Support for several PHY interfaces
    • Media Independent Interface Management access to PHY registers
  • ARINC 664 (AFDX) End System DO-254 IP Core
    • The ARINC 664 (AFDX) End System DO-254 IP Core (AFDX ES IP) implements an AFDX End System as specified in ARINC 664 Part 7 “Avionics Full-Duplex Switched Ethernet (AFDX) Network”.
    • The AFDX ES IP supports MII, RMII, GMII or SGMII as PHY interfaces. Therefore, it is able to transmit and receive at 10 Mbps, 100 Mbps or 1000 Mbps, making full usage of the bandwidth.
    Block Diagram -- ARINC 664 (AFDX) End System DO-254 IP Core
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