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10 100 1000M Ethernet PHY IP

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  • MAC 10/100/1000 Ethernet Controller
    • IEEE 802.3-2002 specification with preamble, start-of-frame delimiter (SFD), frame padding generation and cyclic redundancy code (CRC) generation and checking is fully implemented
    • Supports 10/100 Mbps or 1000 Mbps operation (selectable via a core configuration registers)
    • Supports full- and half-duplex operation (selectable via a core configuration registers)
    • CSMA/CD protocol for half-duplex operation
    Block Diagram -- MAC 10/100/1000 Ethernet Controller
  • DO-254 10/100/1000 Ethernet MAC
    • Configurable bit rate (1000 Mb/s, 100 Mb/s or 10 Mb/s)
    • DAL A according to DO-254 / ED-80
    • Compliant to the following clauses of the IEEE 802.3-2008 specification:
    • Compliant to the RMII specification (March 20, 1998)
    Block Diagram -- DO-254 10/100/1000 Ethernet MAC
  • Serial Gigabit Media Independent Interface
    • Offers a reduced pin-count interface between MII or GMII Ethernet MACs and Physical Layer devices
    • Supports Revision 1.7 of the Serial GMII specification
    • Supports MII 10/100 Mbps and GMII 1000 Mbps Ethernet speeds
    • Supports Full Duplex transfers at all speeds, and Half Duplex at 10/100Mbps
  • GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in SAM 14LPP
    • EEE 802.3-2008, IEEE 802.3az fully standards compliant
    • IEEE 1588-2008 support
    • BroadR-Reach™ support
    • Dual port MAC interface:
    Block Diagram -- GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in SAM 14LPP
  • XPS_LL_TEMAC
    • Independent 2K, 4K, 8K, 16K, or 32K Byte TX and RX data FIFOs for queueing frames
    • Filtering of "bad" receive frames
    • Support for several PHY interfaces
    • Media Independent Interface Management access to PHY registers
  • Tri-Mode Ethernet Media Access Controller (TEMAC)
    • Designed to IEEE 802.3-2012 specification
    • Supports 10/100/1000/2500 Mbps Ethernet
    • Configurable half-duplex and full-duplex operation
    • Configured and monitored through an optional independent microprocessor-neutral interface
  • Ethernet 1G/2.5G BASE-X PCS/PMA or SGMII
    • Designed to IEEE 802.3-2012 specification
    • Full-duplex operation
    • Supports speeds up to 2.5 Gigabit per second
    • Supports Select I/O or Transceiver implementations
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