NetTimeLogic’s PPS Clock to PPS core is a full hardware (FPGA) only implementation of a PPS generator out of a clock of configurable frequency, it is intended to be connected to a PPS Slave core able to syntonize to a Pulse per Second. The core also checks if the input clock is in the configured range and only if so will generate a PPS. The core can be configured either by signals or by an AXI4Lite-Slave Register interface.
This core is intended to be used with either external clocks or also SyncE clocks when the frequency shall be adjusted numerically rather than a clock switch.
Pulse Per Second (PPS) Clock to PPS core
Overview
Key Features
- Configurable input frequency from 100Hz to 100MHz
- Input frequency supervision
- PPS duty cycle configurable in ms steps
- PPS Generation runs directly on Input Clock (minimal Jitter)
- AXI4Lite register set or static configuration
Benefits
- Coprocessor handling PPS generation standalone in the core.
- Wide frequency input and runtime configurable.
- Allows to have a syntonized clock even if the input clock is gone
- Simple interface
Block Diagram
Applications
- Legacy Networks
- Time converters
- Robot control
- Distributed data acquisition
- Test and measurement
Deliverables
- Source Code (not encrypted, not obfuscated)
- Reference Designs
- Testbench with Stimulifiles
- Configuration Tool
- Documentation
Technical Specifications
Availability
Now
Related IPs
- Pulse Per Second Slave (PPS) core
- Pulse Per Second Master (PPS) core
- I2C Controller IP – Slave, SCL Clock, Parameterized FIFO, APB Bus. For low power requirements in I2C Slave Controller interface to CPU
- Differential Clock Receiver to CML on TSMC CLN2P
- Differential Clock Receiver to CML on TSMC CLN3E
- Differential Clock Receiver to CML on TSMC CLN3P-CLN3X