A2B System Interconnect
Overview
A2B is a high performance system bus designed for use in synthesizable designs. It is specifically developed to meet the challenges of multiprocessor and multiple DMA / IO processor, System-on-chip designs. A2B is designed to have the highest possible bus occupancy so that the sustainable bus bandwidth closely approaches the available peak bandwidth of a given configuration.
Key Features
- 8-bit through any power of 2 data width
- Any width for addresses
- Virtual and Physical addressing support
- Clock rate is implementation dependant
- Fully synchronous operation
- Multiple byte and burst mode data transfers
- True Split transaction mode for high bus occupancy
- Split read/write bus mode for high performance
- Programmable arbitration mechanism
- Available extensions:
- Parity protection on any or all buses
- Multiprocessing protocols -- including cache coherency
- Virtual addressing and translation
- Address burst / Complex addressing
- Error and Retry protocols
- Additional User-defined bus fields
Deliverables
- Verilog RTL
- Verilog Testbench & development environment
Technical Specifications
Maturity
Production
Availability
now