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Ultra Low Power Embedded SRAM - Samsung 28FDSOI
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
- Configurable mux factor sets column length and overall aspect ratio
- Bit Line Voltage control eliminates potential low operating voltages issues
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Ultra Low Power Embedded SRAM - TSMC 22ULL
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
- Configurable mux factor sets column length and overall aspect ratio
- Bit Line Voltage control eliminates potential low operating voltages issues
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Ultra Low Voltage Embedded SRAM - TSMC 22ULL
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
- ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
- Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
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Ultra Low Power Embedded SRAM - TSMC 28HPC+
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
- Configurable mux factor sets column length and overall aspect ratio
- Bit Line Voltage control eliminates potential low operating voltages issues
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Ultra Low Voltage Embedded SRAM - TSMC 28HPC+
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
- ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
- Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
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Ultra Low Voltage Embedded SRAM - TSMC 40ULP
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
- ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
- Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
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RAM 8b, 16b, and 32b data widths - TSMC 180nm
- 8b, 16b, and 32b data widths available.
- Up to 250MHz clock operation.
- Read and write data busses may tie for single bus operation.
- Available production test RTL.
- VDD 1.6V – 2.0V.
- Data retention to 0.9V.
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Xccela PSRAM Memory Model
- Supports Xccela PSRAM memory devices from all leading vendors
- Supports 100% of Xccela PSRAM protocol standard
- Supports all the Xccela PSRAM commands as per the specs
- Supports below Low Power Features
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Xccela Flash Memory Model
- Supports Xccela Flash memory devices like MT35X_QLJW_U_256_ABA/ MT35X_QLKA_L_01G_BBA/ MT35X_QLKA_U_02G_CBA from all leading vendors
- Supports 100% of Xccela Flash protocol Standards.
- Supports all the Xccela Flash commands as per the specs.
- Supports Single and double transfer rate (SDR/DDR)
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Wide Range VCC Flash Memory Model
- Supports Wide Range VCC Flash memory devices like MX25R3235F, MX25R1635F, MX25R6435 from all leading vendors
- Supports 100% of Wide Range VCC Flash protocol standards.
- Supports all the Wide Range VCC Flash commands as per the specs.
- Supports Serial Peripheral Interface - Mode 0 and Mode 3
