USB IP

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Compare 438 USB IP from 47 vendors (1 - 10)
  • USB 2.0 PHY GlobalFoundaries 12nm, 22nm, 28nm, 40nm
    • Complies with USB specifications Rev. 2.0 and 1.1
    • Complies with UTMI+ specification Level 3, Rev. 1.0
    • Supports 480Mb/s (HS), 12Mb/s (FS) and 1.5MB/s (LS) serial data transmission rates
    • Supports 8-bit unidirectional Parallel Interface Engine (PIE) bus for HS, FS and LS modes, and Serial Interface Engine (SIE) for FS and LS modes
    Block Diagram -- USB 2.0 PHY GlobalFoundaries 12nm, 22nm, 28nm, 40nm
  • USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm
    • Complies with USB specifications Rev. 2.0 and 1.1
    • Complies with UTMI+ specification Level 3, Rev. 1.0
    • Supports 480Mb/s (HS), 12Mb/s (FS) and 1.5MB/s (LS) serial data transmission rates
    • Supports 8-bit unidirectional Parallel Interface Engine (PIE) bus for HS, FS and LS modes, and Serial Interface Engine (SIE) for FS and LS modes
    Block Diagram -- USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm
  • Complete USB Type-C Power Delivery PHY, RTL, and Software
    • USB PD 3.1 compliant.
    • 8 bit register interface for a low speed processor, or optional I2C interface.
    • Integrated Chapter 6 protocol reduces required MPU response time to 10mS.
    Block Diagram -- Complete USB Type-C Power Delivery  PHY, RTL, and Software
  • USB 2.0 PHY IP, Silicon Proven in TSMC 22ULP
    • Compliant with USB2.0 and USB1.1 specification
    • Compliant with UTMI Specification Version level 3.
    • Supports HS(480Mbps)/FS(12Mbps) /LS(1.5Mbps) modes
    • All required terminations, including 1.5Kohm pullup on DP and DM, and 15Kohm pull-down on DP and DM are internal to chip
    Block Diagram -- USB 2.0 PHY IP, Silicon Proven in TSMC 22ULP
  • USB 2.0 OTG High / Full / Low- Speed Dual Role IP Core
    • Support SW controlled host/device role switching.
    • Support Fullspeed and Lowspeed
    • Support Control, Bulk, Interrupt and Isochronous Transfer Types
    • Support L1/L2 power saving modes for USB 2.0 port
    Block Diagram -- USB 2.0 OTG High / Full / Low- Speed Dual Role IP Core
  • MIPI M-PHY - TSMC 40nm
    • Compliant to MIPI Alliance Standard for M-PHY specification Version 3.0
    • •Supports high speed data transfer G1A/B, G2A/B and G3A/B with data rates of up to 5830.4 Mbps
    • •Supports M-PHY Type-I system
    • •Support for reference clock frequencies of 19.2MHz/26MHz/38.4MHz/52MHz
    Block Diagram -- MIPI M-PHY - TSMC 40nm
  • USB 2.0 PHY
    • Complies with USB specifications, rev. 2.0 and 1.1
    • Complies with UTMI+ specification, level 3, rev. 1.0
    • Supports 480Mb/s (HS), 12Mb/s (FS) and 1.5MB/s (LS) serial data transmission rates
    • Supports 8-bit unidirectional Parallel Interface Engine (PIE) bus for HS, FS and LS modes, and Serial Interface Engine (SIE) for FS and LS modes
    Block Diagram -- USB 2.0 PHY
  • USB2.0 PHY, 8-bit or a 16-bit parallel interface, remaining backward compatible with USB1.1 legacy protocol at 12Mbps
    • Complies with Universal Serial Bus Specification Rev. 2.0
    • Interface compliant with the UTMI specification (60MHz 8-bit interface or 30MHz 16-bit interface)
    • Supports 480Mbps High-Speed(HS) and 12Mbps Full-Speed(FS)
    Block Diagram -- USB2.0 PHY, 8-bit or a 16-bit parallel interface, remaining backward compatible with USB1.1 legacy protocol at 12Mbps
  • SD4.1 UHS- II PHY IP
    • SD 4.1 compliant SDHC/SDXC UHS-II Physical Layer for Host
    • 16bit interface to Link layer
    • Supports both Full Duplex mode and Half Duplex mode
    Block Diagram -- SD4.1 UHS- II PHY IP
  • USB 2.0 On-chip oscillator, termination resistors, and DP/DM short circuit protection (0.18u)
    • On-chip oscillator, termination resistors, and DP/DM short circuit protection.
    • Low pin count
    • Minimum number of external
    • components
    Block Diagram -- USB 2.0 On-chip oscillator, termination resistors, and DP/DM short circuit protection (0.18u)
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