UALink IP Cores

Welcome to the ultimate UALink IP hub! Explore our vast directory of UALink IP cores.

UALink 1.0 IP Cores will enable up to 200Gbps per lane scale-up connection for up to 1024 accelerators within an AI pod.

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Compare 4 UALink IP Cores from 3 vendors (1 - 4)

UALink PCS IP Core
- The UA Link PCS IP Core is a high-performance, silicon-agnostic and fully compliant Physical Coding Sublayer (PCS) implementation of UALink_200 specification.
- Designed for seamless integration into accelerator, switch, and SoC designs, it delivers deterministic low-latency, robust error correction, and compatibility with multiple high-speed Ethernet-derived link rates.
Verification IP for UALink
- API based transaction flow for ease of use
- Specification linked Protocol checks and functional coverage
- Exceptions, callback, error injection and analysis ports for Scoreboard
- TLM ports at each layer for traffic tracing
- Configurable timers for threshold testing
224G SerDes PHY and controller for UALink for AI systems
- UALink, the standard for AI accelerator interconnects, facilitates this scalability by providing low-latency, high-bandwidth communication.
- As a member of the UALink Consortium, Cadence offers verified UALink IP subsystems, including controllers and silicon-proven PHYs, optimized for robust performance in both short and long-reach applications and delivering industry-leading power, performance, and area (PPA).
UALink IP Solution
- Lightweight, low latency IP solution for XPU to XPU interconnects optimized for AI workloads
- Fully integrated IP solution for AI accelerators (XPUs), GPUs, and switches
- Enables maximum throughput with up to 200Gbps per lane
- Supports memory sharing capabilities to expand compute and memory resources from XPU to XPU