UALink IP Cores

Welcome to the ultimate UALink IP hub! Explore our vast directory of UALink IP cores.

UALink 1.0 IP Cores will enable up to 200Gbps per lane scale-up connection for up to 1024 accelerators within an AI pod.

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224G SerDes PHY and controller for UALink for AI systems
- UALink, the standard for AI accelerator interconnects, facilitates this scalability by providing low-latency, high-bandwidth communication.
- As a member of the UALink Consortium, Cadence offers verified UALink IP subsystems, including controllers and silicon-proven PHYs, optimized for robust performance in both short and long-reach applications and delivering industry-leading power, performance, and area (PPA).
UALink IP Solution
- Lightweight, low latency IP solution for XPU to XPU interconnects optimized for AI workloads
- Fully integrated IP solution for AI accelerators (XPUs), GPUs, and switches
- Enables maximum throughput with up to 200Gbps per lane
- Supports memory sharing capabilities to expand compute and memory resources from XPU to XPU