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JESD204 IP

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Compare 40 JESD204 IP from 11 vendors (1 - 10)
  • JESD204D Controller IP
    • Line rates up to 116 Gbps
    • Supports 1-24 lanes
    • Supports 1-96 converters
    • HD-mode supported
    Block Diagram -- JESD204D Controller IP
  • JESD204C Controller IP
    • Designed to JEDEC JESD204C.1 specification
    • Line rates from 1 Gbps to 32.5 Gbps
    • Supports 1-24 lanes
    • Supports 1-96 converters
    Block Diagram -- JESD204C Controller IP
  • JESD204B Controller IP
    • Designed to JEDEC JESD204B.01 specification
    • Line rates from 1 Gbps to 12.5 Gbps (with optional extension to 16 Gbps)
    • Supports 1-24 lanes
    • Supports 1-96 converters
    Block Diagram -- JESD204B Controller IP
  • JESD204D Transmitter and Receiver IP
    • Designed according to JEDEC JESD204D Standard.
    • Supports up to 24 lanes per IP cores.
    • Supports new link layer using Reed-Solomon Forward Error Correction (RS-FEC).
    • Option for backward compatibility to JESD204C (supports 64B/66B encoding) and JESD204B (supports 8B/10B encoding).
    Block Diagram -- JESD204D Transmitter and Receiver IP
  • JESD204C Transmitter and Receiver
    • With the addition of error correction and Detection(FEC, CRC), cutting-edge instrumentation and other applications can operate without any errors.
    • Offers better DC balance, clock recovery and data alignment compared to JESD204B.
    • The bit overhead is 3.125% which is much smaller than JESD204B (~ 25%).
    • Provides interface for serializing devices from some system designs, reducing space, power, and cost.
    Block Diagram -- JESD204C Transmitter and Receiver
  • JESD204B Transmitter and Receiver
    • Applicable in RADAR, Medical Imaging as it supports higher bandwidth and more number of channels with fewer pins to simplify layout.
    • Applicable in Wireless Communications, TDMA & OFDM based technologies such as LTE, WiMAX can benefit from high frequency scalability provided by JESD204B.
    • JESD204B is necessary for high density systems as it provides reduced PCB area and package size.
    • Comparable power for large throughput.
    Block Diagram -- JESD204B Transmitter and Receiver
  • JESD403 VIP
    • Compliant with JESD403 version 1.0 specification.
    • Full JESD403 Host Controller and Device functionality.
    • Two wire serial interface up to 12.5 MHz.
    • Supports Dynamic Address Assignment including Static Addressing for legacy I2C Devices.
    Block Diagram -- JESD403 VIP
  • JESD207 Verification IP
    • Supports JESD207 specification.
    • Operates as BBIC (Baseband IC) and RFIC (Radio front end IC) monitor.
    • Supports half duplex data transfer.
    • Supports DDR source synchronous data transfer timing.
    Block Diagram -- JESD207 Verification IP
  • JESD204 Verification IP
    • Follows JESD204 specification JESD204A, JESD204B, JESD204C and JESD204D.
    • Supports Transmitter and Receiver Mode.
    • Supports data interfaces up to 116 Gbps with PAM4 and up to 58 Gbps with PAM2 in PHY layer.
    • Supports up to 32 lanes.
    Block Diagram -- JESD204 Verification IP
  • JESD207 Synthesizable Transactor
    • Follows JESD207 specification
    • Supports BBIC and RFIC Mode
    • Supports half duplex data transfer
    • Supports DDR source synchronous data transfer timing
    Block Diagram -- JESD207 Synthesizable Transactor
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