Interface IP Cores for TSMC

Welcome to the ultimate Interface IP Cores for TSMC hub! Explore our vast directory of Interface IP Cores for TSMC
All offers in Interface IP Cores for TSMC
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Compare 710 Interface IP Cores for TSMC from 35 vendors (1 - 10)
  • 24-bit -130dB THD+N Multi-Channel Audio Sample Rate Converter
    • This core can be used to interface digital audio equipments operating at different sample rates.
    • It has been designed for systems requiring very high quality in terms of low harmonic distortion and noise, tolerance and rejection of input jitter.
    Block Diagram -- 24-bit -130dB THD+N Multi-Channel Audio Sample Rate Converter
  • 16-bit -90dB THD+N Multi-Channel Audio Sample Rate Converter
    • This core can be used to interface digital audio equipments operating at different sample rates.
    • It has been designed for systems that require a low-cost solution, maintaining low harmonic distortion and noise, and a high tolerance and rejection of input jitter.
    Block Diagram -- 16-bit -90dB THD+N Multi-Channel Audio Sample Rate Converter
  • MIPI I3C Target Device
    • MIPI I3C Basic Specification v1.2 compiliance
    • Native 32-bit CPU Interface
    • Optional CPU interface wrappers (APB, AHB, AXI)
    • Legacy I2C communication with 7-bit Static Address
    • I3C Single Data Rate (SDR) mode
    Block Diagram -- MIPI I3C Target Device
  • USB Full Speed Transceiver
    • Exceeds USB 2.0 Full Speed specification.
    • Trimmed pull up resistor.
    • Enable / suspend feature.
    • DPF and UFP options available.
    Block Diagram -- USB Full Speed Transceiver
  • Complete USB Type-C Power Delivery IP
    • Mixed signal Analog Front End Macros for 65n, 130n, 150nm, and 180n technologies.
    • RTL code from AFE to I2C compatible register set.
    • Stand alone C code for Protocol, Device Policy Manager, and System Policy Manager.
    • IP demonstration & development board, with compliance reports. 
    • Full chip integration of USB Type-C, and associated software.
    Block Diagram -- Complete USB Type-C Power Delivery  IP
  • PCIe 6.0 PHY, TSMC N3A x4 1.2V, North/South (vertical) poly orientation for Automotive, ASIL B Random, AEC-Q100 Grade 2
    • Supports the latest features of PCIe 6.x and CXL 3.x specifications
    • Supports PAM-4 signaling and up to x16 lane configurations with bifurcation
    • Delivers more power efficiency across channels with unique DSP algorithms
    • Enables near zero link downtime with patent-pending diagnostic features
    Block Diagram -- PCIe 6.0 PHY, TSMC N3A x4 1.2V, North/South (vertical) poly orientation for Automotive, ASIL B Random, AEC-Q100 Grade 2
  • USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
    • Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
    • Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
    • x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
    • Low active and standby power
    • Small area for low silicon cost
    Block Diagram -- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
  • USB4 PHY - TSMC N4P 1.2V, North/South Poly Orientation
    • Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
    • Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
    • x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
    • Low active and standby power
    • Small area for low silicon cost
    Block Diagram -- USB4 PHY - TSMC N4P 1.2V, North/South Poly Orientation
  • USB4 PHY - TSMC N3P 1.2V, North/South Poly Orientation
    • Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
    • Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
    • x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
    • Low active and standby power
    • Small area for low silicon cost
    Block Diagram -- USB4 PHY - TSMC N3P 1.2V, North/South Poly Orientation
  • USB4 PHY - TSMC N3E 1.2V, North/South Poly Orientation
    • Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
    • Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
    • x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
    • Low active and standby power
    • Small area for low silicon cost
    Block Diagram -- USB4 PHY - TSMC N3E 1.2V, North/South Poly Orientation
×
Semiconductor IP