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Interface IP Cores for TSMC

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Compare 729 Interface IP Cores for TSMC from 37 vendors (1 - 10)
  • MIPI D-PHY RX+ (Receiver) IP
    • The MIPI® D-PHY RX+ is a proprietary implementation of the MIPI Camera Serial Interface 2 (CSI-2) and Display Serial Interface (DSI) D-PHY Receiver.
    • It is optimized to achieve full-speed production testing, in-system testing, and higher performance compared to traditional configurations, while reducing area and standby power.
    Block Diagram -- MIPI D-PHY RX+ (Receiver) IP
  • 4.25 Gbps Multi-Standard SerDes
    • The MXL4254A is a silicon proven Quad Gigabit SerDes implemented in digital CMOS technology. Each of the four channels supports data rate up to 4.25 Gbps.It is compatible with router-backplane links, PCI Express, SATA, RapidIO, 10 Gbps Ethernet (XAUI), FibreChannel, SFI-5, SPI-5, and other communication applications.
    Block Diagram -- 4.25 Gbps Multi-Standard SerDes
  • MIPI D-PHY/LVDS Combo Receiver IP
    • The MXL-LVDS-MIPI-RX is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Standard for D-PHY and compatible with the TIA/EIA-644 LVDS standard.
    • The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display serial interface applications (DSI).
    Block Diagram -- MIPI D-PHY/LVDS Combo Receiver IP
  • MIPI D-PHY/LVDS Combo Transmitter IP
    • The MXL-LVDS-DPHY-DSI-TX is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI® Alliance Standard for D-PHY and a high performance 4-channel LVDS Serializer implemented using digital CMOS technology.
    • In LVDS mode, both the serial and parallel data are organized into 4 channels. The parallel data is 7 bits wide per channel. The input clock is 25MHz to 150MHz. The serializer is highly integrated and requires no external components. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
    Block Diagram -- MIPI D-PHY/LVDS Combo Transmitter IP
  • MIPI D-PHY IP
    • The D-PHY is partitioned into a Digital Module – CIL (Control and Interface Logic) and a Mixed Signal Module. It is provided as a combination of Soft IP views (RTL, and STA Constraints) for Digital Module, and Hard IP views (GDSII/CDL/LEF/LIB) for the Mixed Signal Module.
    • This unique offering of Soft and Hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow.
    Block Diagram -- MIPI D-PHY IP
  • MIPI M-PHY IP
    • The MIPI M-PHY is a high-frequency low-power, Physical Layer IP that supports the MIPI® Alliance Standard for M-PHY.
    • The IP can be used as a physical layer for many applications, connecting flash memory-based storage, cameras and RF subsystems, and for providing chip-to-chip inter-processor communications (IPC).
    Block Diagram -- MIPI M-PHY IP
  • PCI Express PIPE PHY Transceiver
    • Supports 2.5Gb/s serial data rate
    • Utilizes 8-bit or 16-bit parallel interface to transmit and receive PCI Express data
    • Full Support for Auxiliary Power (Vaux) for Energy aware systems like Multi-Port Host Controllers
    • Data and clock recovery from serial stream on the PCI Express bus
    Block Diagram -- PCI Express PIPE PHY Transceiver
  • PCIe Gen2 PHY
    • PCI Express Gen 2 and Gen 1 compliant
    • Supports various PCI Express modes and extensions
    • Programmable amplitude and pre-emphasis
    • Programmable receiver equalization
    Block Diagram -- PCIe Gen2 PHY
  • PCI v2.1 Master/Slave controller
    • The PCI master/slave controller is fully compliant with PCI Local Bus Specification, Revision 2.3.
    • It has a fully customizable PCI Configuration Space. The controller supports both 32- and 64-bit PCI bus paths.
    • The application interface can be configured as a 32-bit bit as well as a 64-bit interface as per requirements.
    Block Diagram -- PCI v2.1 Master/Slave controller
  • PCI v2.1 Host Controller
    • The PCI Host controller offers a PCI 32-bit bus operating at 33MHz and supports PCI devices conforming to the PCI Local Bus Specification 2.1.
    • PCI Host Bridge contains an internal arbiter to manage up to 4 external devices 
    Block Diagram -- PCI v2.1 Host Controller
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