Interface IP Cores for TSMC

Ultra-low-latency round-trip (fiber-to-fiber or gate-to-gate) for 10 Gigabit Ethernet, first-bit to first-bit
Reconciliation sub-layer implementation compliant with IEEE802.3
Local fault and remote fault detection and handling
Frame Check Sequence (FCS) insertion and verification at line rate

The TCP Endpoint implements a full, reliable streaming network stack in FPGA logic.
It allows applications in logic to be directly connected to Internet Protocol (IP) interfaces by opening, maintaining, and closing TCP Connections via Ethernet to other hardware or software endpoints.

The ApolloCORE(MR/VSR) Multi-Standard-Serdes (MSS) IP is optimized for Medium Reach (MR) and Very Short Reach (VSR) applications.
It is a highly configurable IP that supports all leading edge NRZ and PAM data center standards from 1Gbps to 112Gbps.

The MIPI^® D-PHY RX+ is a proprietary implementation of the MIPI Camera Serial Interface 2 (CSI-2) and Display Serial Interface (DSI) D-PHY Receiver.
It is optimized to achieve full-speed production testing, in-system testing, and higher performance compared to traditional configurations, while reducing area and standby power.

The MXL4254A is a silicon proven Quad Gigabit SerDes implemented in digital CMOS technology. Each of the four channels supports data rate up to 4.25 Gbps.It is compatible with router-backplane links, PCI Express, SATA, RapidIO, 10 Gbps Ethernet (XAUI), FibreChannel, SFI-5, SPI-5, and other communication applications.

The MXL-LVDS-MIPI-RX is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI^® Alliance Standard for D-PHY and compatible with the TIA/EIA-644 LVDS standard.
The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display serial interface applications (DSI).

The MXL-LVDS-DPHY-DSI-TX is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI^® Alliance Standard for D-PHY and a high performance 4-channel LVDS Serializer implemented using digital CMOS technology.
In LVDS mode, both the serial and parallel data are organized into 4 channels. The parallel data is 7 bits wide per channel. The input clock is 25MHz to 150MHz. The serializer is highly integrated and requires no external components. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.

The D-PHY is partitioned into a Digital Module – CIL (Control and Interface Logic) and a Mixed Signal Module. It is provided as a combination of Soft IP views (RTL, and STA Constraints) for Digital Module, and Hard IP views (GDSII/CDL/LEF/LIB) for the Mixed Signal Module.
This unique offering of Soft and Hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow.

The MIPI M-PHY is a high-frequency low-power, Physical Layer IP that supports the MIPI^® Alliance Standard for M-PHY.
The IP can be used as a physical layer for many applications, connecting flash memory-based storage, cameras and RF subsystems, and for providing chip-to-chip inter-processor communications (IPC).

Supports 2.5Gb/s serial data rate
Utilizes 8-bit or 16-bit parallel interface to transmit and receive PCI Express data
Full Support for Auxiliary Power (Vaux) for Energy aware systems like Multi-Port Host Controllers
Data and clock recovery from serial stream on the PCI Express bus